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Spartan-3E FPGA Starter Kit Board User Guide

UG230 (v1.2) January 20, 2011

Appendix B:

Example User Constraints File (UCF)

NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

# ==== PS/2 Mouse/Keyboard Port (PS2) ====

NET "PS2_CLK" LOC = "G14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

# ==== Rotary Pushbutton Switch (ROT) ====

NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ;

NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ;

NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;

# ==== RS-232 Serial Ports (RS232) ====

NET "RS232_DCE_RXD" LOC = "R7" | IOSTANDARD = LVTTL ;

NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;

NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL ;

NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;

# ==== DDR SDRAM (SD) ==== (I/O Bank 3, VCCO=2.5V)

NET "SD_A<0>" LOC = "T1" | IOSTANDARD = SSTL2_I ;

NET "SD_A<1>" LOC = "R3" | IOSTANDARD = SSTL2_I ;

NET "SD_A<2>" LOC = "R2" | IOSTANDARD = SSTL2_I ;

NET "SD_A<3>" LOC = "P1" | IOSTANDARD = SSTL2_I ;

NET "SD_A<4>" LOC = "F4" | IOSTANDARD = SSTL2_I ;

NET "SD_A<5>" LOC = "H4" | IOSTANDARD = SSTL2_I ;

NET "SD_A<6>" LOC = "H3" | IOSTANDARD = SSTL2_I ;

NET "SD_A<7>" LOC = "H1" | IOSTANDARD = SSTL2_I ;

NET "SD_A<8>" LOC = "H2" | IOSTANDARD = SSTL2_I ;

NET "SD_A<9>" LOC = "N4" | IOSTANDARD = SSTL2_I ;

NET "SD_A<10>" LOC = "T2" | IOSTANDARD = SSTL2_I ;

NET "SD_A<11>" LOC = "N5" | IOSTANDARD = SSTL2_I ;

NET "SD_A<12>" LOC = "P2" | IOSTANDARD = SSTL2_I ;

NET "SD_BA<0>" LOC = "K5" | IOSTANDARD = SSTL2_I ;

NET "SD_BA<1>" LOC = "K6" | IOSTANDARD = SSTL2_I ;

NET "SD_CAS" LOC = "C2" | IOSTANDARD = SSTL2_I ;

NET "SD_CK_N" LOC = "J4" | IOSTANDARD = SSTL2_I ;

NET "SD_CK_P" LOC = "J5" | IOSTANDARD = SSTL2_I ;

NET "SD_CKE" LOC = "K3" | IOSTANDARD = SSTL2_I ;

NET "SD_CS" LOC = "K4" | IOSTANDARD = SSTL2_I ;

NET "SD_DQ<0>" LOC = "L2" | IOSTANDARD = SSTL2_I ;

NET "SD_DQ<1>" LOC = "L1" | IOSTANDARD = SSTL2_I ;

NET "SD_DQ<2>" LOC = "L3" | IOSTANDARD = SSTL2_I ;

NET "SD_DQ<3>" LOC = "L4" | IOSTANDARD = SSTL2_I ;

NET "SD_DQ<4>" LOC = "M3" | IOSTANDARD = SSTL2_I ;

NET "SD_DQ<5>" LOC = "M4" | IOSTANDARD = SSTL2_I ;

NET "SD_DQ<6>" LOC = "M5" | IOSTANDARD = SSTL2_I ;

NET "SD_DQ<7>" LOC = "M6" | IOSTANDARD = SSTL2_I ;

NET "SD_DQ<8>" LOC = "E2" | IOSTANDARD = SSTL2_I ;

NET "SD_DQ<9>" LOC = "E1" | IOSTANDARD = SSTL2_I ;

NET "SD_DQ<10>" LOC = "F1" | IOSTANDARD = SSTL2_I ;

NET "SD_DQ<11>" LOC = "F2" | IOSTANDARD = SSTL2_I ;

NET "SD_DQ<12>" LOC = "G6" | IOSTANDARD = SSTL2_I ;

NET "SD_DQ<13>" LOC = "G5" | IOSTANDARD = SSTL2_I ;

NET "SD_DQ<14>" LOC = "H6" | IOSTANDARD = SSTL2_I ;

NET "SD_DQ<15>" LOC = "H5" | IOSTANDARD = SSTL2_I ;

Summary of Contents for Xilinx UG230

Page 1: ...R Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 2 January 20 2011 ...

Page 2: ...MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DESIGN INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE TITLE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOST DATA AND LOST PROFITS ARISING FROM OR RELATING TO YOUR USE OF THE D...

Page 3: ...ages for all Applications 13 Related Resources 13 Chapter 2 Switches Buttons and Knob Slide Switches 15 Locations and Labels 15 Operation 15 UCF Location Constraints 15 Push Button Switches 16 Locations and Labels 16 Operation 16 UCF Location Constraints 17 Rotary Push Button Switch 17 Locations and Labels 17 Operation 17 Push Button Switch 17 Rotary Shaft Encoder 18 UCF Location Constraints 19 Di...

Page 4: ...Programming the Platform Flash PROM 38 Related Resources 41 Chapter 5 Character LCD Screen Overview 43 Character LCD Interface Signals 44 Voltage Compatibility 44 Interaction with Intel StrataFlash 44 UCF Location Constraints 45 LCD Controller 45 Memory Map 45 DD RAM 45 CG ROM 46 CG RAM 47 Command Set 48 Disabled 49 Clear Display 49 Return Cursor Home 49 Entry Mode Set 49 Display On Off 50 Cursor ...

Page 5: ... Digital to Analog Converter DAC SPI Communication 69 Interface Signals 70 Disable Other Devices on the SPI Bus to Avoid Contention 70 SPI Communication Details 71 Communication Protocol 71 Specifying the DAC Output Voltage 72 DAC Outputs A and B 72 DAC Outputs C and D 72 UCF Location Constraints 73 Related Resources 73 Chapter 10 Analog Capture Circuit Digital Outputs from Analog Inputs 76 Progra...

Page 6: ...OM File 93 Setting the Configuration Clock Rate 93 Formatting an SPI Flash PROM File 94 Downloading the Design to SPI Flash 97 Downloading the SPI Flash 98 Attach a JTAG Parallel Programming Cable 98 Insert Jumper on JP8 and Hold PROG_B Low 99 Additional Design Details 100 Shared SPI Bus with Peripherals 100 Other SPI Flash Control Signals 101 Variant Select Pins VS 2 0 101 Jumper Block J11 101 Pr...

Page 7: ...5 Related Resources 126 Chapter 16 XC2C64A CoolRunner II CPLD UCF Location Constraints 129 FPGA Connections to CPLD 129 CPLD 129 Related Resources 130 Chapter 17 DS2432 1 Wire SHA 1 EEPROM UCF Location Constraints 131 Related Resources 131 Appendix A Schematics FX2 Expansion Header 6 pin Headers and Connectorless Probe Header 134 RS 232 Ports VGA Port and PS 2 Port 136 Ethernet PHY Magnetics and R...

Page 8: ... xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 2 January 20 2011 R DDR SDRAM Series Termination and FX2 Connector Differential Termination 158 Appendix B Example User Constraints File UCF ...

Page 9: ...r regulators for the non FPGA components Micron Technology Inc for the 32M x 16 DDR SDRAM SMSC for the 10 100 Ethernet PHY STMicroelectronics for the 16M x 1 SPI serial Flash PROM Texas Instruments Incorporated for the three rail TPS75003 regulator supplying most of the FPGA supply voltages Xilinx Inc Configuration Solutions Division for the XCF04S Platform Flash PROM and their support for the emb...

Page 10: ...DR SDRAM describes the functionality of the DDR SDRAM Chapter 14 10 100 Ethernet Physical Layer Interface describes the functionality of the 10 100Base T Ethernet physical layer interface Chapter 15 Expansion Connectors describes the various connectors available on the Spartan 3E FPGA Starter Kit board Chapter 16 XC2C64A CoolRunner II CPLD describes how the CPLD is involved in FPGA configuration w...

Page 11: ...ides a convenient development board for embedded processing applications The board highlights these features Spartan 3E FPGA specific features Parallel NOR Flash configuration MultiBoot FPGA configuration from Parallel NOR Flash PROM SPI serial Flash configuration Embedded development MicroBlaze 32 bit embedded RISC processor PicoBlaze 8 bit embedded controller DDR memory interfaces Advanced Spart...

Page 12: ...on SPI_MOSI on the rising edge of the SPI_SCK clock signal The amplifier presents serial data on AMP_DOUT on the falling edge of SPI_SCK 5 0 0 1 1 1 4 1 9 10 0 1 0 0 1 525 1 775 20 0 1 0 1 1 5875 1 7125 50 0 1 1 0 1 625 1 675 100 0 1 1 1 1 6375 1 6625 Table 10 2 Programmable Gain Settings for Pre Amplifier Continued Gain A3 A2 A1 A0 Input Voltage Range B3 B2 B1 B0 Minimum Maximum Figure 10 3 SPI S...

Page 13: ...0 6 provides an example SPI bus transaction to the ADC When the AD_CONV signal goes High the ADC simultaneously samples both analog channels The results of this conversion are not presented until the next time AD_CONV is asserted a latency of one sample The maxim sample rate is approximately 1 5 MHz The ADC presents the digital representation of the sampled analog values as a 14 bit two s compleme...

Page 14: ...3 D0 D5 D6 D7 D4 D9 D10 D11 D8 D13 D12 D1 D2 D3 D0 D5 D6 D7 D4 D9 D10 D11 D8 D13 D12 Z Z Z 13 13 0 0 SPI_MISO SPI_SCK AD_CONV 13 Channel 0 Channel 0 Channel 1 Sample point Sample point Converted data is presented with a latency of one sample The sampled analog value is converted to digital data 32 SPI_SCK cycles after asserting AD_CONV The converted values is then presented after the next AD_CONV ...

Page 15: ... for Master Serial mode configuration Connecting Analog Inputs Connect AC signals to VINA or VINB via a DC blocking capacitor Related Resources Amplifier and A D Converter Control for the Spartan 3E Starter Kit Reference Design http www xilinx com s3estarter Xilinx PicoBlaze Soft Processor http www xilinx com picoblaze LTC6912 Dual Programmable Gain Amplifiers with Serial Digital Interface http ww...

Page 16: ...82 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 2 January 20 2011 Chapter 10 Analog Capture Circuit R ...

Page 17: ...Stores two different FPGA configurations in the StrataFlash device and dynamically switch between the two using the Spartan 3E FPGA s MultiBoot feature Stores and executes MicroBlaze processor code directly from the StrataFlash device Figure 11 1 Connections to Intel StrataFlash Flash Memory CE2 CE1 CE0 OE WE BYTE D 15 12 D 11 8 A 24 20 A 19 0 STS D 0 LDC0 LDC1 HDC LDC2 User I O User I O D 0 User ...

Page 18: ...uires just slightly over 2 Mbits per configuration image the FPGA to StrataFlash interface on the board support up to a 256 Mbit StrataFlash The Spartan 3E FPGA Starter Kit board ships with a 128 Mbit device Address line SF_A24 is not used In general the StrataFlash device connects to the XC3S500E to support Byte Peripheral Interface BPI configuration The upper four address bits from the FPGA A 23...

Page 19: ...e pins during FPGA configuration as described in Chapter 16 XC2C64A CoolRunner II CPLD Also connects to FPGA user I O pins SF_A24 is the same as FX2 connector signal FX2_IO 32 SF_A23 N11 SF_A22 V12 SF_A21 V13 SF_A20 T12 SF_A19 V15 Connects to FPGA pins A 19 0 to support the BPI configuration SF_A18 U15 SF_A17 T16 SF_A16 U18 SF_A15 T17 SF_A14 R18 SF_A13 T18 SF_A12 L16 SF_A11 L15 SF_A10 K13 SF_A9 K1...

Page 20: ...F_D3 V9 SF_D2 R10 SF_D1 P10 SPI_MISO N10 Bit 0 of data byte and 16 bit halfword Connects to FPGA pin D0 DIN to support the BPI configuration Shared with other SPI peripherals and Platform Flash PROM Control SF_CE0 D16 StrataFlash Chip Enable Connects to FPGA pin LDC0 to support the BPI configuration SF_WE D17 StrataFlash Write Enable Connects to FPGA pin HDC to support the BPI configuration SF_OE ...

Page 21: ...significant address line SF_A 24 is not physically used on the 16 Mbyte StrataFlash PROM It is provided for upward migration to a larger StrataFlash PROM in the same package footprint Likewsie the SF_A 24 signal is also connected to the FX2_IO 32 signal on the FX2 expansion connector SPI Data Line The least significant StrataFlash data line SF_D 0 is shared with data output signals from serial SPI...

Page 22: ...33 DRIVE 4 SLEW SLOW NET SF_A 9 LOC K12 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_A 8 LOC K15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_A 7 LOC K14 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_A 6 LOC J17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_A 5 LOC J16 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_A 4 LOC J15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_A 3 LOC J14 IOSTANDARD LVCMOS3...

Page 23: ...nd Character LCD SW0 SW1 SW2 and SW3 are slide switches Push button switches W E S and N are located around the ROT1 push button switch rotary encoder LD0 through LD7 are discrete LEDs See Chapter 2 Switches Buttons and Knob for additional information DISP1 is a 2x16 character LCD screen See Chapter 5 Character LCD Screen for additional information ...

Page 24: ...Spartan 3E FPGA Starter Kit Board User Guide www xilinx com 157 UG230 v1 2 January 20 2011 Buttons Switches Rotary Encoder and Character LCD R Figure A 12 Schematic Sheet 13 UG230_Aa_12_021806 ...

Page 25: ...ntial Termination Resistors R160 through R201 represent the series termination resistors for the DDR SDRAM See Chapter 13 DDR SDRAM for additional information Resistors R202 through R210 are not loaded on the board These landing pads provide optional connections for 100Ωdifferential termination resistors See Using Differential Inputs page 120 for additional information ...

Page 26: ...n 3E FPGA Starter Kit Board User Guide www xilinx com 159 UG230 v1 2 January 20 2011 DDR SDRAM Series Termination and FX2 Connector Differential Termination R Figure A 13 Schematic Sheet 14 UG230_Aa_13_021806 ...

Page 27: ...160 www xilinx com Spartan 3E FPGA Starter Kit Board User Guide UG230 v1 2 January 20 2011 Appendix A Schematics R ...

Page 28: ...DARD LVTTL PULLDOWN NET BTN_NORTH LOC V4 IOSTANDARD LVTTL PULLDOWN NET BTN_SOUTH LOC K17 IOSTANDARD LVTTL PULLDOWN NET BTN_WEST LOC D18 IOSTANDARD LVTTL PULLDOWN Clock inputs CLK NET CLK_50MHZ LOC C9 IOSTANDARD LVCMOS33 Define clock period for 50 MHz oscillator 40 60 duty cycle NET CLK_50MHZ PERIOD 20 0ns HIGH 40 NET CLK_AUX LOC B8 IOSTANDARD LVCMOS33 NET CLK_SMA LOC A10 IOSTANDARD LVCMOS33 Digita...

Page 29: ...DARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_IO 2 LOC A4 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_IO 3 LOC D5 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_IO 4 LOC C5 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 These four connections are shared with the J2 6 pin accessory header NET FX2_IO 5 LOC A6 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_IO 6 LOC B6 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_I...

Page 30: ...der J2 These are shared connections with the FX2 connector NET J2 0 LOC A6 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J2 1 LOC B6 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J2 2 LOC E7 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J2 3 LOC F7 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 6 pin header J4 These are shared connections with the FX2 connector NET J4 0 LOC D7 IOSTANDARD LVTTL SLEW SLOW DRIVE 6 NET J4 1 LOC C7 IO...

Page 31: ...NDARD SSTL2_I NET SD_A 5 LOC H4 IOSTANDARD SSTL2_I NET SD_A 6 LOC H3 IOSTANDARD SSTL2_I NET SD_A 7 LOC H1 IOSTANDARD SSTL2_I NET SD_A 8 LOC H2 IOSTANDARD SSTL2_I NET SD_A 9 LOC N4 IOSTANDARD SSTL2_I NET SD_A 10 LOC T2 IOSTANDARD SSTL2_I NET SD_A 11 LOC N5 IOSTANDARD SSTL2_I NET SD_A 12 LOC P2 IOSTANDARD SSTL2_I NET SD_BA 0 LOC K5 IOSTANDARD SSTL2_I NET SD_BA 1 LOC K6 IOSTANDARD SSTL2_I NET SD_CAS ...

Page 32: ...STANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_A 15 LOC T17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_A 16 LOC U18 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_A 17 LOC T16 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_A 18 LOC U15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_A 19 LOC V15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_A 20 LOC T12 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET SF_A 21 LOC ...

Page 33: ...PULLUP NET SW 1 LOC L14 IOSTANDARD LVTTL PULLUP NET SW 2 LOC H18 IOSTANDARD LVTTL PULLUP NET SW 3 LOC N17 IOSTANDARD LVTTL PULLUP VGA Port VGA NET VGA_BLUE LOC G15 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA_GREEN LOC H15 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA_HSYNC LOC F15 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA_RED LOC H14 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA_VSYNC LOC F14 IOSTANDARD...

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