Texas Instruments Xilinx UG230, User Manual

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Spartan-3E FPGA Starter Kit Board User Guide www.xilinx.com 81
UG230 (v1.2) January 20, 2011
Disable Other Devices on the SPI Bus to Avoid Contention
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Disable Other Devices on the SPI Bus to Avoid Contention
The SPI bus signals are shared by other devices on the board. It is vital that other devices
are disabled when the FPGA communicates with the AMP or ADC to avoid bus
contention.
Table 10-4 provides the signals and logic values required to disable the other
devices. Although the StrataFlash PROM is a parallel device, its least-significant data bit is
shared with the SPI_MISO signal. The Platform Flash PROM is only potentially enabled if
the FPGA is set up for Master Serial mode configuration.
Connecting Analog Inputs
Connect AC signals to VINA or VINB via a DC blocking capacitor.
Related Resources
• Amplifier and A/D Converter Control for the Spartan-3E Starter Kit (Reference
Design)
http://www.xilinx.com/s3estarter
• Xilinx PicoBlaze Soft Processor
http://www.xilinx.com/picoblaze
• LTC6912 Dual Programmable Gain Amplifiers with Serial Digital Interface
http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1154,C1009,C1121,P7596,D5359
• LTC1407A-1 Serial 14-bit Simultaneous Sampling ADCs with Shutdown
http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1001,C1158,P2420,D1295
Table 10-4: Disable Other Devices on SPI Bus
Signal Disabled Device Disable Value
SPI_SS_B SPI Serial Flash 1
AMP_CS Programmable Pre-Amplifier 1
DAC_CS DAC 1
SF_CE0 StrataFlash Parallel Flash PROM 1
FPGA_INIT_B Platform Flash PROM 0