NOTE:
4. EN must be deasserted at least 10 µs before VBAT or VIO supply can be lowered (order of supply turn off
NOTE:
after EN shutdown is immaterial).
NOTE:
5. EXT_32K - Fail safe I/O
Figure 8-2. Power-Up System
8.19.3 Chip Top-level Power-Up Sequence
shows the top-level power-up sequence for the chip.
VBAT / VIO
input
EXT_32K
input
WL_EN
input
Main 1V8 DC2DC
TCXO_CLK_REQ
output
DIG DC2DC
SRAM LDO
Internal power stable = 5 ms
Top RESETZ
4.5 ms delay
Figure 8-3. Chip Top-Level Power-Up Sequence
WL1801MOD, WL1805MOD, WL1831MOD, WL1835MOD
SWRS152N – JUNE 2013 – REVISED APRIL 2021
Copyright © 2021 Texas Instruments Incorporated
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