Texas Instruments UCC14240EVM-052 User Manual Download | Manualshive

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User’s Guide

Using the UCC14240EVM-052 for Biasing Traction Inverter
Gate Driver ICs Requiring Single, Positive or Dual,
Positive/Negative Bias Power

ABSTRACT

This user’s guide provides a description and directions for the use of the UCC14240EVM-052 to evaluate the
UCC14240-Q1, high frequency, integrated transformer, DC-DC converter module from Texas Instruments. This
EVM allows designers to quickly and efficiently evaluate the UCC14240-Q1 for use in automotive or industrial
applications requiring gate driver IC bias power, meeting up to 3 kVRMS isolation.

Table of Contents

1 Introduction

.............................................................................................................................................................................

1.1 Pin Configuration and Functions........................................................................................................................................

2 Description

..............................................................................................................................................................................

2.1 EVM Electrical Performance Specifications.......................................................................................................................

3 Schematic

................................................................................................................................................................................

4 EVM Setup and Operation

......................................................................................................................................................

4.1 Reference...........................................................................................................................................................................

4.2 External Connections for Easy Evaluation.........................................................................................................................

4.3 Powering the EVM.............................................................................................................................................................

4.4 EVM Test Points...............................................................................................................................................................

4.5 Oscilloscope Probes: Probing the EVM............................................................................................................................

5 Performance Data

................................................................................................................................................................

5.1 Efficiency Data.................................................................................................................................................................

5.2 Regulation Data...............................................................................................................................................................

5.3 Start-up Waveforms.........................................................................................................................................................

5.4 Inrush Current..................................................................................................................................................................

5.5 AC Ripple Voltage............................................................................................................................................................

5.6 EN and /PG Timing..........................................................................................................................................................

5.7 Shutdown.........................................................................................................................................................................

5.8 Steady State.....................................................................................................................................................................

5.9 Thermal Performance......................................................................................................................................................

6 Assembly and Printed Circuit Board (PCB) Layers

...........................................................................................................

7 Bill of Materials (BOM)

..........................................................................................................................................................

8 Revision History

...................................................................................................................................................................

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Table of Contents

SLUUCJ2 – JULY 2021

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Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs

Requiring Single, Positive or Dual, Positive/Negative Bias Power

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Copyright © 2021 Texas Instruments Incorporated

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Summary of Contents for UCC14240EVM-052

Page 1: ...rmance Specifications 5 3 Schematic 6 4 EVM Setup and Operation 7 4 1 Reference 7 4 2 External Connections for Easy Evaluation 7 4 3 Powering the EVM 8 4 4 EVM Test Points 10 4 5 Oscilloscope Probes Probing the EVM 11 5 Performance Data 12 5 1 Efficiency Data 12 5 2 Regulation Data 14 5 3 Start up Waveforms 15 5 4 Inrush Current 17 5 5 AC Ripple Voltage 18 5 6 EN and PG Timing 19 5 7 Shutdown 20 5...

Page 2: ...imary to the secondary side while removing the need for bulky external transformers or power modules commonly used in existing designs This integration allows for a much smaller printed circuit board PCB area as well as a much lower height profile when compared to industry standards for power isolation techniques used in the field today Introduction www ti com 2 Using the UCC14240EVM 052 for Biasi...

Page 3: ... a parallel 150 pF ceramic capacitor from VDD to VEE The 150 pF is the high frequency bypass and should be next to the IC RLIM 32 P Secondary side second isolated output voltage resistor to limit the source current from VDD to COM node and the sink current from COM to VEE Connect a resistor from RLIM to COM to regulate the COM VEE voltage FBVEE 33 I Feedback COM VEE output voltage sense pin used t...

Page 4: ...VEE 0 V and easily apply variable loads to the outputs This EVM allows the user to measure efficiency across the input voltage range and varying output loads that the system might require Another feature of the EVM is the ease of probing during test Test points are strategically placed and described according to Table 4 2 Figure 2 1 UCC14240EVM 052 HVP052E1p1 Top View Figure 2 2 UCC14240EVM 052 HV...

Page 5: ...mA 0 107 VDD pk to pk AC ripple IVDD 80 mA 200 250 mV VDDSS Soft start IVDD IVEE 0 mA 1 8 ms PMAX Maximum output power IVDD 100 mA IVEE 10 mA 1 5 2 W VEE DC full load set point 21 V VIN 27 V IVEE 10 mA 5 061 5 062 V IVEE VDD load current range 21 V VIN 27 V 0 10 mA VEE pk to pk AC ripple IVEE 10 mA 75 90 mV SYSTEM CHARACTERISTICS η Full load efficiency IVDD 80 mA 59 η Half load efficiency IVDD 40 ...

Page 6: ... VEE VIN GNDP VBIAS GNDP GNDP VBIAS ENA PG GNDP GNDP 49 9k 0 1 R4 VEE VEE 50V 100pF C1 G TP4 FBVDD SH J1 50V 100pF C2 ENA VEE VEEA Ground Tie 100k R5 FBVEE VEE TP1 TP5 FBVDD FBVEE 1 2 J1 1 2 J5 1 2 3 J2 VIN 6 VIN 7 VEE 26 VEE 27 VDD 28 VDD 29 RLIM 32 FBVEE 33 FBVDD 34 VEEA 35 GNDP 5 GNDP 1 PG 3 GNDP 2 ENA 4 GNDP 8 GNDP 9 GNDP 10 GNDP 11 GNDP 12 GNDP 13 GNDP 14 GNDP 15 GNDP 16 GNDP 17 GNDP 18 VEE 1...

Page 7: ...ENA Turn off disable the 5V DC Bias power supply 3 Connect the VIN DC power supply capable of 21 V VIN 27 V 200 mA at J5 1 2 VIN Adjust the power supply to 24 V and set the current limit to 300 mA Set the power supply to 24 V Turn off disable the VIN power supply 4 Connect a variable load between J2 1 VDD and J2 3 VEE If using an electronic load set to constant current CC 80 mA Leave the load disa...

Page 8: ...tart up signals shown in Figure 4 4 Adding the RC filter inverts the ENA logic as described in Table 4 1 such that removing the jumper turns ON the EVM with controlled ENA and inserting the EN jumper into J3 1 2 OFF turns OFF the EVM Applying the shorting jumper to J3 2 3 ON has no effect even though the RC filter is applied as shown in Figure 4 3 Figure 4 2 ENA Erratic Signal Bounce Causing VDD C...

Page 9: ... EN ON position 3 Turn on the VIN DC power supply Verify 24 V is present at TP8 to TP9 4 Verify the loads on VDD and VEE are disabled 5 Turn on the 5 V DC bias power supply EVM is now enabled with VDD and VEE in regulation under no load conditions 6 Verify 20 V is present on VDD and 5 V is present on VEE 7 Enable the 80 mA load on VDD enable the 10 mA load on VEE 8 The UCC14240 Q1 is now regulatin...

Page 10: ...Green Secondary VDD to VEE 15 27 V J2 2 3 O Green Secondary COM to VEE 0 5 V J3 1 2 I Black EN off 0 V J3 2 3 I Black EN on VBIAS V J4 N A N A Missing reference designator N A J5 I Green VIN primary input voltage 21 24 27 V TP1 TP Black VEE secondary side reference 0 V TP2 TP Yellow PG power good test point VBIAS V TP3 TP Yellow EN enable test point VBIAS V TP4 TP PCB COM to VEE secondary COM scop...

Page 11: ...a gate driver IC VDD VDD COM and VEE VEE COM are referred to with respect to COM In this case consider COM to be GND as it acts as a virtual GND to the gate driver IC Because the midpoint of the capacitive divider is sensitive to charge imbalance do not connect any ground referenced test equipment to TP5 COM when probing the EVM A battery powered DVM can be used to measure VEE with respect to COM ...

Page 12: ...98 15 10 5 06 1 48 0 81 54 50 21 01 85 98 20 16 50 31 15 10 5 06 1 81 1 01 56 15 21 01 100 92 20 16 60 20 15 10 5 06 2 12 1 21 57 23 21 01 115 65 20 16 69 86 15 10 5 06 2 43 1 41 57 95 21 01 131 00 20 15 80 10 15 09 5 06 2 75 1 61 58 65 21 01 145 92 20 15 89 98 15 09 5 06 3 07 1 81 59 14 21 01 161 25 20 14 100 09 15 08 5 06 3 39 2 02 59 50 21 01 175 99 20 13 109 84 15 07 5 06 3 70 2 21 59 80 21 01...

Page 13: ... VISO V IISO mA VISO1 V VISO2 V PIN W PISO W Eff 27 02 9 88 20 19 0 24 15 13 5 06 0 27 0 00 1 81 27 02 15 69 20 18 5 07 15 12 5 06 0 42 0 10 24 14 27 02 22 02 20 18 10 24 15 12 5 06 0 59 0 21 34 75 27 01 34 75 20 18 20 57 15 12 5 06 0 94 0 42 44 21 27 01 46 73 20 18 30 06 15 12 5 06 1 26 0 61 48 04 27 01 59 12 20 17 40 04 15 12 5 06 1 60 0 81 50 58 27 01 71 94 20 17 50 33 15 11 5 06 1 94 1 02 52 2...

Page 14: ...40EVM Regulation vs Current VISO Loading Only Performance Data www ti com 14 Using the UCC14240EVM 052 for Biasing Traction Inverter Gate Driver ICs Requiring Single Positive or Dual Positive Negative Bias Power SLUUCJ2 JULY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Page 15: ...t up 2 VIN 24 V IISO 80 mA top VISO 10V div mid 1 COM 5V div mid 2 VDD VISO COM 10V div bot VEE COM 5V div time 2ms div unless otherwise noted www ti com Performance Data SLUUCJ2 JULY 2021 Submit Document Feedback Using the UCC14240EVM 052 for Biasing Traction Inverter Gate Driver ICs Requiring Single Positive or Dual Positive Negative Bias Power 15 Copyright 2021 Texas Instruments Incorporated ...

Page 16: ...herwise noted Figure 5 7 Start up 4 VIN 24 V IISO 80 mA top VISO 10V div bot COM 2V div time 2ms div unless otherwise noted Performance Data www ti com 16 Using the UCC14240EVM 052 for Biasing Traction Inverter Gate Driver ICs Requiring Single Positive or Dual Positive Negative Bias Power SLUUCJ2 JULY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Page 17: ...m top VISO 10V div mid 1 COM 5V div mid 2 IIN 0 1A div mid 3 PG 5V div mid 4 VISO 6 2V div 305µs div bot IIN 0 05A div 305µs div time 2ms div unless otherwise noted www ti com Performance Data SLUUCJ2 JULY 2021 Submit Document Feedback Using the UCC14240EVM 052 for Biasing Traction Inverter Gate Driver ICs Requiring Single Positive or Dual Positive Negative Bias Power 17 Copyright 2021 Texas Instr...

Page 18: ...mA FSW pri 12 9 MHz top VISO 0 1V div mid 1 COM 0 02V div mid 2 COM 0 02V divc 100ns div bot VISO 5mV div 100ns div time 5µs div unless otherwise noted Performance Data www ti com 18 Using the UCC14240EVM 052 for Biasing Traction Inverter Gate Driver ICs Requiring Single Positive or Dual Positive Negative Bias Power SLUUCJ2 JULY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorp...

Page 19: ... 13 ENA to PG Delay 4 2 ms IVDD 80 mA top ENA 5V div mid PG 5V div bot VDD 10V div time 2ms div unless otherwise noted www ti com Performance Data SLUUCJ2 JULY 2021 Submit Document Feedback Using the UCC14240EVM 052 for Biasing Traction Inverter Gate Driver ICs Requiring Single Positive or Dual Positive Negative Bias Power 19 Copyright 2021 Texas Instruments Incorporated ...

Page 20: ...Shutdown EN Low VIN 24 V IVDD 80 mA top VISO 10V div mid 1 COM 2V div mid 2 VDD VISO COM 10V div mid 3 VEE COM 5V div mid 4 PG 5V div bot ENA 5V div time 2ms div unless otherwise noted Performance Data www ti com 20 Using the UCC14240EVM 052 for Biasing Traction Inverter Gate Driver ICs Requiring Single Positive or Dual Positive Negative Bias Power SLUUCJ2 JULY 2021 Submit Document Feedback Copyri...

Page 21: ...O2 5V div mod 4 IIN 0 2A div bot VIN 20V div time 2ms div unless otherwise noted www ti com Performance Data SLUUCJ2 JULY 2021 Submit Document Feedback Using the UCC14240EVM 052 for Biasing Traction Inverter Gate Driver ICs Requiring Single Positive or Dual Positive Negative Bias Power 21 Copyright 2021 Texas Instruments Incorporated ...

Page 22: ...24 V VDD 20 24 V IVDD 80 mA VVEE 5 V IVEE 10 mA POUT 1 67 W TRISE 35 5 C see Equation 2 Figure 5 18 Rated Power TRISE 60 5 C 25 C 35 5 C 2 Performance Data www ti com 22 Using the UCC14240EVM 052 for Biasing Traction Inverter Gate Driver ICs Requiring Single Positive or Dual Positive Negative Bias Power SLUUCJ2 JULY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Page 23: ...nal layers but similar design methodology such as the use of stitch vias internal ground planes and not routing is the isolation region between GNDP and GNDS should be applied as best as possible Figure 6 1 UCC14240EVM 052 Fully Assembled 3D Top View www ti com Assembly and Printed Circuit Board PCB Layers SLUUCJ2 JULY 2021 Submit Document Feedback Using the UCC14240EVM 052 for Biasing Traction In...

Page 24: ...gle View Assembly and Printed Circuit Board PCB Layers www ti com 24 Using the UCC14240EVM 052 for Biasing Traction Inverter Gate Driver ICs Requiring Single Positive or Dual Positive Negative Bias Power SLUUCJ2 JULY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Page 25: ...e as layer 3 www ti com Assembly and Printed Circuit Board PCB Layers SLUUCJ2 JULY 2021 Submit Document Feedback Using the UCC14240EVM 052 for Biasing Traction Inverter Gate Driver ICs Requiring Single Positive or Dual Positive Negative Bias Power 25 Copyright 2021 Texas Instruments Incorporated ...

Page 26: ...ssembly mirrored view Assembly and Printed Circuit Board PCB Layers www ti com 26 Using the UCC14240EVM 052 for Biasing Traction Inverter Gate Driver ICs Requiring Single Positive or Dual Positive Negative Bias Power SLUUCJ2 JULY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Page 27: ...onik J3 1 Header 100mil 3x1 TH PEC03SAAN Sullins LBL1 1 Thermal Transfer Printable Labels 0 650 W x 0 200 H PCB Label THT 14 423 10 Brady R1 1 10 0 kΩ RES Thin Film 0 1 0 1 W AEC Q200 Grade 0 0603 ERA 3ARB103V Panasonic R2 R4 2 49 9 kΩ RES Thin Film 0 1 0 1 W AEC Q200 Grade 0 0603 ERA 3AEB4992V Panasonic R3 1 69 8 kΩ RES Thin Film 0 1 0 1 W AEC Q200 Grade 0 0603 ERA 3AEB6982V Panasonic R5 1 100 kΩ...

Page 28: ... DC Converter SOIC36 UCC14240DWNQ 1 Texas Instruments C6 0 10 µF CAP CER 35 V 10 X7R AEC Q200 Grade 1 1206 CGA5L1X7R1V10 6K160AC TDK 8 Revision History NOTE Page numbers for previous revisions may differ from page numbers in the current version DATE REVISION NOTES Initial Release Revision History www ti com 28 Using the UCC14240EVM 052 for Biasing Traction Inverter Gate Driver ICs Requiring Single...

Page 29: ...s are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you wi...

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