5.8 Steady State
Figure 5-16. Steady State, VIN=24 V, IVDD=80 mA, (top: VISO1, 20V/div, mid-1: VISO2, 5V/div, mid-2:
VISO1-VISO2, 20V/div, mid-3: -VISO2, 5V/div, mod-4: IIN, 0.2A/div, bot: VIN, 20V/div), time = 2ms/div
unless otherwise noted.
Performance Data
SLUUCJ2 – JULY 2021
Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs
Requiring Single, Positive or Dual, Positive/Negative Bias Power
21
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