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Software Operation
•
FIR B– B side first FIR filter in high-pass mode when set, low-pass mode when cleared.
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Dual Clk– Only used when the PLL is disabled. When set, two differential clocks are used to input the
data to the chip; CLK1/CLK1C is used to latch the input data into the chip, and CLK2/CLK2C is used
as the DAC sample clock.
•
Interleave– When set, interleaved input data mode is enabled; both A and B data streams are input at
the DA(15:0) input pins.
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Inverse Sinc– Enables inverse sinc filter.
•
Half Rate Input– Enables half rate input mode. Input data for the DAC A data path is input to the chip
at half speed using both the DA(15:0) and DB(15:0) input pins.
•
Sif– Sets sif_4-pin bit. A 4-pin serial interface mode is enabled when on, 3-pin mode when off. The
DAC5687 Demo Kit is configured for a 3-pin serial interface, so setting to a 4-bit serial interface makes
reading registers impossible with the GUI.
•
Inv. PLL Lock– Only used when PLL is disabled and dual clock mode is disabled. When cleared, input
data is latched into the chip on rising edges of the PLLLOCK output pin. When set, input data is
latched into the chip on falling edges of the PLLLOCK output pin.
•
PLL Freq– Sets PLL VCO center frequency to low or high center frequency.
•
PLL Kv– Sets PLL VCO gain to either high or low gain.
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Qflag– Sets qflag bit. When set, the QFLAG input pin operates as a B sample indicator when
interleaved data is enabled. When cleared, the TXENABLE rising determines the A/B timing
relationship.
•
2's Comp– When set, input data is interpreted as 2's complement. When cleared, input data is
interpreted as offset binary.
•
Rev A Bus– When cleared, DA input data MSB to LSB order is DA(15) = MSB and DA(0) = LSB.
When set, DA input data MSB to LSB order is reversed, DA(15) = LSB and DA(0) = MSB.
•
Rev B Bus– When cleared, DB input data MSB to LSB order is DB(15) = MSB and DB(0) = LSB.
When set, DB input data MSB to LSB order is reversed, DB(15) = LSB and DB(0) = MSB.
•
USB– When set, the data to DACB is inverted to generate upper side band output.
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Inv. Clk I(Q)– Inverts the DAC core sample clock when set, normal when cleared.
•
Sync_Phstr– When set, the internal clock divider logic is initialized with a PHSTR pin low to high
transition.
•
Sync_cm– When set, the coarse mixer is synchronized with a PHSTR low-to-high transition.
•
Sync_NCO– When set, the NCO phase accumulator is cleared with a phstr low-to-high transition.
•
Phstr Clk Div Select– Selects the clock used to latch the PHSTR input when restarting the internal
clock dividers. When set, the full rate CLK2 signal latches PHSTR and when cleared, the divided down
input clock signal latches PHSTR.
•
DAC Serial Data– When set, both DAC A and DAC B input data is replaced with fixed data loaded into
the 16-bit serial interface DAC Static Data.
–
Counter Mode– Controls the internal counter that can be used as the DAC data source: {off; all
16b; 7b LSBs; 5b MIDs; 5b MSBs}.
–
DAC Static Data– When DAC Serial Data is set, both DAC A and DAC B input data is replaced
with fixed data loaded with this value. Range = 0 - 65535.
•
Alt. PLLLOCK Output– Can be used to determine alternate outputs on the PLLLOCK pin when using
the internal PLL mode. The EXTLO pin must be open when using this mode.
•
NCO– When set, enables NCO.
–
NCO Gain– Sets NCO gain resulting in a 2x increase in NCO output amplitude. Except for F
s
/2 and
F
s
/4 mixing NCO frequencies, this selection can result in saturation for full-scale inputs. Consider
using QMC gain for lower gains.
•
QMC– When set, enables the QMC.
–
QMCA Gain– Sets QMC gain A to a range = 0 to 2047. See the data sheet for more information.
–
QMC B Gain– Sets QMC gain B to a range = 0 to 2047. See the data sheet for more information.
–
QMC Phase– Sets QMC phase to a range = -512 to 511. See the data sheet for more information.
Used to adjust for I/Q phase imbalance.
•
Mode– Used to select the coarse mixer mode. See the DAC5687 data sheet for more information.
SLWU013A – March 2004 – Revised September 2005
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