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11.1

Layers

Layers and Schematics

The Demo Kit is constructed on a 6-layer, 6.2 inch x 8 inch, 0.062-inch thick PCB using FR-4 material.
See

through

show the PCB layout for the Demo Kit.

Figure 13. Top Layer

26

SLWU013A – March 2004 – Revised September 2005

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Summary of Contents for TSW3000

Page 1: ...TSW3000 Demo Kit User s Guide September 2005 SLWU013A ...

Page 2: ...TSW3000 Demo Kit User s Guide Literature Number SLWU013A March 2004 Revised September 2005 ...

Page 3: ...ions 14 6 Board Setup 16 6 1 Jumper Settings 16 6 2 Input Output Connectors 17 6 3 Parallel Port 17 6 4 DC Power Requirements 17 7 Demo Kit Test Configuration 17 7 1 Test Setup Block Diagram 18 7 2 Test Equipment 18 7 3 Calibration 18 7 4 Test Specifications 18 8 Basic Test Procedure 19 8 1 Initial Inspection 19 8 2 Engage Power Supplies 19 8 3 Program the CDCM7005 19 8 4 Program the TRF3750 19 8 ...

Page 4: ...10 Filter Specifications 25 10 1 Baseband Filter 25 11 Layers and Schematics 25 11 1 Layers 26 11 2 Schematics 35 Contents 4 SLWU013A March 2004 Revised September 2005 ...

Page 5: ...efault DAC GUI With fDAC 8 Tone From NCO 21 10 Single Sideband Spectrum Output Before DAC Offset and QMC Adjustments 22 11 DAC GUI With Typical Settings To Minimize LO and Sideband 23 12 Sideband and LO 24 13 Top Layer 26 14 Top Layer NH 27 15 Layer 2 28 16 Layer 3 29 17 Layer 4 30 18 Layer 4 NH 31 19 Layer 5 32 20 Bottom Layer 33 21 Bottom Silkscreen 34 22 Drill Drawing 35 SLWU013A March 2004 Rev...

Page 6: ...s 1 Frequency Bands 7 2 CDCM7005 Register Values 11 3 Jumper List 16 4 Input Output Connections 17 5 Demo Kit Specifications 18 6 Frequency Designations 19 List of Tables 6 SLWU013A March 2004 Revised September 2005 ...

Page 7: ... the TRF370x modulator By design in order to preserve the proper dc levels the DAC gain should be kept at maximum 15 though deviation by a few steps is generally acceptable with no degradation in performance The CDCM7005 requires a VCXO source to derive its output clock signals The VCXO is at reference designator U10 on the back side of the board The frequency of the VCXO can be changed to operate...

Page 8: ...basic radio system block diagram in Figure 1 demonstrates where the TSW3000 Demo Kit fits in the overall transceiver The dash line box illustrates the components found on the TSW3000 Demo Kit board Figure 1 System Block Diagram The basic Demo Kit block diagram is shown in Figure 2 The shaded boxes illustrate the key Texas Instruments components found on the TSW3000 Demo Kit board Figure 2 Demo Kit...

Page 9: ...voltage at baseband or low IF frequencies and outputs an RF signal based on the LO drive frequency The TRF3750 is a PLL chip used in the synthesizer section to generate the LO frequency required for the I Q modulator This section summarizes the installation procedures for the software required to operate the Demo Kit Once all of the software is loaded it is recommended to reboot the computer Extra...

Page 10: ... Kit Executing the program brings up the interface seen in Figure 4 The default settings are correct for a VCXO of 491 52 MHz and a 10 MHz reference as on the TSW3000 The CDCM7005 GUI allows register settings to be saved and can be loaded back in afterwards This can be accomplished with the Save and Load Settings buttons near the right side of the GUI It is recommended that any unused output clock...

Page 11: ...ters are determined by the reference frequency and the VCXO frequency The OUT_MUX sets the divide ratios for the individual output clocks The OUTSEL determines whether the output clocks will be used as single ended CMOS or differential LVPECL With a 10 MHz reference oscillator the CDCM7005 settings are shown in Table 2 for a variety of common VCXO frequencies For other frequencies see to the CDCM7...

Page 12: ... PFD the reference frequency and the prescaler selection The software then displays the actual VCO frequency PFD frequency and the R N A and B counter values to be programmed into the TRF3750 Hitting the Send button writes these values to the TRF3750 In default mode on a default board only the desired VCO frequency 2100 MHz to 2200 MHz needs to be changed For other VCO ranges other parameters may ...

Page 13: ... to the DAC5687 At first startup of this software it is imperative to select the Pll Port Config button to bring up the parallel port configuration settings From the menu select the TSW3000 setting This configures the port to be compatible with the TSW3000 Once the Demo Kit is powered on with the parallel port configured and connected properly then the GUI shown in Figure 7 is displayed with the d...

Page 14: ...687 This is used to verify settings on the front panel Send All Sends the current front panel registers to the device This is generally only used when the Demo Kit power has recycled or the device has been reset and the user wants to load the displayed settings to the device 5 4 2 Configuration Controls Full Bypass When set all filtering QMC and NCO functions are bypassed FIR Bypass Bypass all int...

Page 15: ... When set DB input data MSB to LSB order is reversed DB 15 LSB and DB 0 MSB USB When set the data to DACB is inverted to generate upper side band output Inv Clk I Q Inverts the DAC core sample clock when set normal when cleared Sync_Phstr When set the internal clock divider logic is initialized with a PHSTR pin low to high transition Sync_cm When set the coarse mixer is synchronized with a PHSTR l...

Page 16: ...n FDAC MHz NCO IF MHz Used to calculate the required NCO DDS value 5 4 5 Additional Control Monitor Registers Version Displays the version of the silicon If a version of 0 is read then the communication is not functioning and an error message will be displayed The TSW3000 Demo Kit has on board jumpers that allow the user to selectively disengage devices as desired The unit is shipped with jumpers ...

Page 17: ...ut A from DAC5687 J19 SMA Optional Q out B from DAC5687 J6 SMA Input for external VCXO for CDCM7005 J7 SMA PLL lock status on DAC5687 J4 SMA Phase synchronization on DAC5687 RF shield covers should be in place over the synthesizer section and the RF modulator section These shields provide isolation of the RF sections on the board The TSW3000 Demo Kit contains a 25 pin parallel port connector J1 to...

Page 18: ...ilent PSA or equivalent This particular piece can measure 70 dBc ACPR with the noise cancellation option active This amount of dynamic range is required to accurately measure the ACPR of the Demo Kit Another spectrum analyzer can be substituted if it achieves as good or better dynamic range Pattern Generator Agilent 16702B Oscilloscope Tektronix 650 or equivalent Used to probe clock output signals...

Page 19: ...O frequency U10 that is on the board Note the VCO frequency band Y3 that is on the board Engage 6 V power supply Verify the current reading is between 0 8 A to 1 3 A when configured with the DAC5687 Use the Default Settings on the CDCM7005 GUI See Section 5 1 This generates a 491 52 MHz clock Set the OUT_MUX_0 2 3 4 to tristate Only OUT_MUX_1 is used for clocking the DAC5687 Hit the GUI Send butto...

Page 20: ...moving the jumper at J15 pins 2 and 3 if not already removed Verify DACA and DACB Coarse Gain is set to 15 Set Mode to 0000 No Coarse Mixing Ensure DAC Offsets and DAC fine gain for both A and B are set to 0 Set the spectrum analyzer as follows Center Freq 2 14 GHz RBW 30 kHz VBW 300 kHz Span 491 52 MHz Attn 5 dB Ref Level 10 dBm 20 SLWU013A March 2004 Revised September 2005 ...

Page 21: ...ter performance by adjusting the dc offset controls on the DAC5687 The default DAC GUI is shown below with the NCO mixer turned on to output a 61 44 MHz tone The output spectrum is illustrated in Figure 10 Figure 9 Default DAC GUI With fDAC 8 Tone From NCO SLWU013A March 2004 Revised September 2005 21 ...

Page 22: ... a step size of 100 Continue tuning After each complete cycle reduce the step size down i e to 10 then to 1 if desired A performance greater that 65 dBc should be achievable Sideband rejection is determined by the two quadrature signals to the modulator being exactly 180 degrees out of phase and exactly the same amplitude Amplitude and phase imbalance between the two paths yield an unwanted lower ...

Page 23: ...nimized Change the QMC A or B gains in increments of 1 until the sideband is minimized The overall performance should be greater than 60 dBc from the other sideband with amplitude and phase corrections Re optimized the dc offset values as required to maintain carrier suppression performance as specified Figure 11 DAC GUI With Typical Settings To Minimize LO and Sideband Sideband and LO are reduced...

Page 24: ...is connects the external LO on J10 to the TRF3702 modulator Remove W6 disengages power to RF amplifier Disable the TRF3750 PLL CE by setting J15 25 26 This puts GND on CE of the TRF3750 and disables the PLL To configure the board for an external reference implement the following modifications Remove R144 this disconnects the on board 10 MHz reference Place R201 0 Ω resistor external reference can ...

Page 25: ...TSW3000 Demo Kit layout provides the opportunity to place components to realize up to a 7th order LC filter The Demo Kit is by default populated with a 500 MHz LC low pass filter to help eliminate DAC images and also out of band clock spurs which may mix into RF frequencies 10 1 1 RF Filter Output Match The TSW3000 Demo Kit layout also provides the opportunity to place a small 3rd order LC filter ...

Page 26: ...atics The Demo Kit is constructed on a 6 layer 6 2 inch x 8 inch 0 062 inch thick PCB using FR 4 material See Figure 13 through Figure 22 show the PCB layout for the Demo Kit Figure 13 Top Layer 26 SLWU013A March 2004 Revised September 2005 ...

Page 27: ...www ti com Layers and Schematics Figure 14 Top Layer NH SLWU013A March 2004 Revised September 2005 27 ...

Page 28: ...www ti com Layers and Schematics Figure 15 Layer 2 28 SLWU013A March 2004 Revised September 2005 ...

Page 29: ...www ti com Layers and Schematics Figure 16 Layer 3 SLWU013A March 2004 Revised September 2005 29 ...

Page 30: ...www ti com Layers and Schematics Figure 17 Layer 4 30 SLWU013A March 2004 Revised September 2005 ...

Page 31: ...www ti com Layers and Schematics Figure 18 Layer 4 NH SLWU013A March 2004 Revised September 2005 31 ...

Page 32: ...www ti com Layers and Schematics Figure 19 Layer 5 32 SLWU013A March 2004 Revised September 2005 ...

Page 33: ...www ti com Layers and Schematics Figure 20 Bottom Layer SLWU013A March 2004 Revised September 2005 33 ...

Page 34: ...www ti com Layers and Schematics Figure 21 Bottom Silkscreen 34 SLWU013A March 2004 Revised September 2005 ...

Page 35: ...www ti com 11 2 Schematics Layers and Schematics Figure 22 Drill Drawing The following figures show the schematic for the TSW3000 Demo Kit SLWU013A March 2004 Revised September 2005 35 ...

Page 36: ...IOUTB1 IOUTB2 SH 2 IOUTA1 SH 3 IOUTA2 SH 3 IOUTB2 SH 3 IOUTB1 SH 3 DB 0 15 1 2 3 4 5 J7 SMA C134 1uF C153 10uF 10V 3 3VA R236 221 R235 110 3 3VA Note 1 Note 1 R237 22 1 CLKIN 1 OE 2 1Y0 3 GND 4 1Y1 5 VDD 3 3V 6 1Y2 7 1Y3 8 U17 CDCV304 R197 22 1 Note 2 2 CHANGE TO 0 OHM FOR 50 OHM LOAD 1 3 2 W5 3 3VA 1 8VD KIT A Note 1 EXT_LO EXT_LO SH 2 PLL_VDD PLL_VDD SH 2 W1 R250 0 R249 0 PHSTR Note 1 SH 2 PHSTR...

Page 37: ...A10 A11 A12 A13 A14 A15 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 J13 34PIN_IDC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 J14 34PIN_IDC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 J15 3 3VA SLEEP TXENABLE TE...

Page 38: ...R239 49 9 R238 49 9 VCM R179 100 R183 100 3 3VA R210 221 R211 221 R190 15 R191 15 R244 49 9 R243 49 9 3 3VA 5VA R212 100 R213 100 1 2 3 4 5 J9 SMA C26 1uF C126 1pF C125 1pF C20 1uF 5VA 5VA GND 1 GND 2 GND 3 LO 4 GND 5 VCC 6 PWD 7 RFOUT 8 GND 9 VCC 10 GND 11 GND 12 QVIN 13 IVIN 14 IREF 15 QREF 16 U11 TRF3702 1 3 2 W2 5VA L17 0 C72 Note 2 C66 Note 2 Note 2 C75 1uF C81 1uF R121 274 R122 18 2 R119 274...

Page 39: ...uF C104 1uF C58 1uF C113 1uF 3 3VCLK C71 01uF C73 1uF R151 10K R149 10K 3 3VCLK 3 3VCLK V_CTRL 1 GND 3 VCC 6 OUT 4 EN 2 OUT_B 5 U10 VCXO1 V_CTRL R126 82 5 R127 82 5 R128 130 R129 130 R141 4 75K R142 162 C91 1uF C92 47uF C88 1000pF R7 1K REF_OSC RESET RESET R124 0 Note 1 CLOCK DISTRIBUTION R161 82 5 R162 82 5 R163 82 5 R164 82 5 R152 130 R153 130 R154 130 R156 130 3 3VCLK 1 2 3 4 5 J3 SMA END OUT C...

Page 40: ...2Y2 7 2Y1 9 1Y4 12 1Y3 14 1Y2 16 1Y1 18 OE2 19 VCC 20 U4 SN74HC241DW R17 10K DATA CLK SDEN1 SDEN2 1OE 1 1A 2 2OE 4 2A 5 1Y 3 2Y 6 GND 7 3Y 8 3A 9 3OE 10 4Y 11 4A 12 4OE 13 VCC 14 U13 SN74LV125AD CTRL_CLK CTRL_DATA CTRL_CLK CTRL_DATA C28 1uF 3 3VA R28 100 R27 100 R29 100 R30 100K R32 100K R31 100K C61 10pF C128 10pF C127 10pF 3 3VA 3 3VA 3 3VA Sh 4 Sh 4 Sh 4 CTRL_LE R155 10K SDIO PLL_LE PLL_DATA PL...

Page 41: ...2 GND 3 NC 4 EN_ 5 IN 6 IN 7 NC 8 GND HSINK 9 GND HSINK 10 GND HSINK 11 GND HSINK 12 OUT 13 OUT 14 FB NC 15 RESET_ 16 NC 17 NC 18 GND HSINK 19 GND HSINK 20 U7 TPS76733QPWP 6V C117 10uF 10V C48 1uF R131 100K GND HSINK 1 GND HSINK 2 GND 3 NC 4 EN_ 5 IN 6 IN 7 NC 8 GND HSINK 9 GND HSINK 10 GND HSINK 11 GND HSINK 12 OUT 13 OUT 14 FB NC 15 RESET_ 16 NC 17 NC 18 GND HSINK 19 GND HSINK 20 U8 TPS76701QPWP...

Page 42: ..._LE PLL_DATA PLL_CLK PLL_CLK PLL_DATA PLL_LE SH 5 SH 5 SH 5 PLL_LCK SH 6 FB2 R111 825 R148 5 62 R112 825 LOCAL_OSC LOCAL_OSC SH 3 Note 1 Note 1 3 2 1 4 U15 SGA 5386 C148 22pF C149 22pF C147 1000pF C146 22pF C144 1uF R146 47 5 R147 47 5 L18 0805CS 220X_B_ E2 FB8 FB9 C161 10uF 10V C151 1uF C158 10pF 5V_PLL FB12 R135 3 92K R202 0 1 2 3 4 5 J10 SMA Note 1 1 2 3 4 5 J8 SMA R201 0 Note 1 TCXO_OUT R225 0...

Page 43: ...tute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is...

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