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Hardware Configuration

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8

SLWU092 – April 2017

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Copyright © 2017, Texas Instruments Incorporated

TSW14J57 JESD204B High-Speed Data Capture and Pattern Generator Card
User's Guide

NOTE:

TRIG_OUT_A, TRIG_OUT_B, TRIG_OUT_C SMAs are used to provide a SYNC signal. The

cables of each trigger signal should have equal length to ensure the trigger signal arrives at
the same time for all boards. TRIG_OUT_B and TRIG_OUT_C are multifunctional SMA
connectors. TRIG_OUT_B and TRIG_OUT_C can be used to provide a primary reference
clock or SYSREF signal by making adjustments to the 0

resistors on the signal path.

3.3.3.2

FPGA Mezzanine Card (FMC+) Connector

The TSW14J57 EVM has one connector to allow for the direct plug in of TI JESD204B serial interface
ADC and DAC EVMs. The specifications for this connector are mostly derived from the ANSI/VITA 57.4
FPGA Mezzanine Card (FMC+) Standard. This standard describes the compliance requirements for a low-
overhead protocol bridge between the IO of a mezzanine card and an FPGA processing device on a
carrier card. This specification is being used by FPGA vendors on their development platforms.

The FMC+ connector, J2, provides the interface between the TSW14J57EVM and the ADC or DAC EVM
under test. This 560-pin Samtec high-speed, high-density connector (part number ASP-184329-01) is
suitable for high-speed differential pairs up to 28 Gbps.

In addition to the JESD204B standard signals, several CMOS single-ended signals and LVDS differential
signals are connected between the FMC+ and FPGA. In the future, these signals may allow the HSDC
Pro GUI to control the SPI serial programming of ADC and DAC EVMs that support this feature. The
connector pinout description is shown in

Table 4

.

Table 4. FMC+ Connector Description of the TSW14J57

FMC+ Signal Name

FMC+ Pin

Standard JESD204

Application Mapping

Description

RX0_P/N

C6 and C7

Lane 0± (M

C)

JESD Serial data transmitted from mezzanine and received
by carrier

RX1_P/N

A2 and A3

Lane 1± (M

C)

JESD Serial data transmitted from mezzanine and received
by carrier

RX2_P/N

A6 and A7

Lane 2± (M

C)

JESD Serial data transmitted from mezzanine and received
by carrier

RX3_P/N

A10 and A11

Lane 3± (M

C)

JESD Serial data transmitted from mezzanine and received
by carrier

RX4_P/N

A14 and A15

Lane 4± (M

C)

JESD Serial data transmitted from mezzanine and received
by carrier

RX5_P/N

A18 and A19

Lane 5± (M

C)

JESD Serial data transmitted from mezzanine and received
by carrier

RX6_P/N

B16 and B17

Lane 6± (M

C)

JESD Serial data transmitted from mezzanine and received
by carrier

RX7_P/N

B12 and B13

Lane 7± (M

C)

JESD Serial data transmitted from mezzanine and received
by carrier

RX8_P/N

B8 and B9

Lane 8± (M

C)

JESD Serial data transmitted from mezzanine and received
by carrier

RX9_P/N

B4 and B5

Lane 9± (M

C)

JESD Serial data transmitted from mezzanine and received
by carrier

RX10_P/N

Y10 and Y11

Lane 10± (M

C)

JESD Serial data transmitted from mezzanine and received
by carrier

RX11_P/N

Z12 and Z13

Lane 11± (M

C)

JESD Serial data transmitted from mezzanine and received
by carrier

RX12_P/N

Y14 and Y15

Lane 12± (M

C)

JESD Serial data transmitted from mezzanine and received
by carrier

RX13_P/N

Z16 and Z17

Lane 13± (M

C)

JESD Serial data transmitted from mezzanine and received
by carrier

RX14_P/N

Y18 and Y19

Lane 14± (M

C)

JESD Serial data transmitted from mezzanine and received
by carrier

RX15_P/N

Y22 and Y23

Lane 15± (M

C)

JESD Serial data transmitted from mezzanine and received
by carrier

Summary of Contents for TSW14J57EVM

Page 1: ...ata Capture 5 2 2 DAC EVM Pattern Generator 5 3 Hardware Configuration 5 3 1 Power Connections 5 3 2 Switches Jumpers and LEDs 6 3 3 LEDs 7 4 Software Start Up 11 4 1 Installation Instructions 11 4 2 USB Interface and Drivers 11 5 Downloading Firmware 14 List of Figures 1 TSW14J57EVM 3 2 TSW14J57 EVM Block Diagram 4 3 Power Indicator LEDs 12 4 TSW14J57EVM Serial Number 12 5 High Speed Data Convert...

Page 2: ... complete system that captures and evaluates data samples from ADC EVMs and generates and sends desired test patterns to DAC EVMs 2 Functionality The TSW14J57EVM has a single industry standard FMC connector that interfaces directly with TI JESD204B ADC and DAC EVMs The FMC carrier connector is compatible with the FMC mezzanine connector When used with an ADC EVM high speed serial data is captured ...

Page 3: ...upport for deterministic latency Serial lanes speeds up to 15 Gbps 16 routed transceiver channels 16Gb DDR4 SDRAM split into four independent 256 16 4Gb SDRAMs Quarter rate DDR4 controllers supporting up to 1200 MHz operation 1G of 16 bit samples of onboard memory Supports 1 8 and 2 5 V CMOS IO standard General purpose 100 MHz oscillator Onboard UCD90120A for power sequencing and monitoring Onboar...

Page 4: ...de Supported by TI HSDC PRO software FPGA firmware developed with Quartus Prime 16 1 and QSYS JESD RX IP core with support for USB and JTAG reconfigurable JESD core parameters L M K F HD S and more ILA configuration data accessible through USB and JTAG Lane alignment and character replacement enabled or disabled through USB and JTAG JESD TX IP core with support for USB and JTAG reconfigurable JESD...

Page 5: ...the guide for more information Several ini files are available to allow the user to load pre determined ADC JESD204B interfaces For example if the user selects the ADC called ADS42JB69_LMF_421 the FPGA will be configured to capture data from the ADS42JB69EVM with the ADC JESD interface configured for 4 lanes 2 converters and 1 octet per frame The TSW14J57 device can capture up to 1G 16 bit samples...

Page 6: ...nd in Table 1 Table 1 Switch Description of the TSW14J57 Device Component Description SW1 Spare dip switches that are connected to spare FPGA inputs SW2 Spare pushbutton that are connected to spare FPGA inputs SW3 Board main power switch SW4 CPU RESET FPGA hardware reset SW5 Power monitor U13 reset SW6 UCD Reset Power monitor U13 reset SW7 Dip switch to set VAR adjustable step down output voltage ...

Page 7: ... are within specification D19 On if DDR_VDD_1 2V_STAT are within specification D21 On if 12V board power is present D22 On if 3 3V is being provided for the power supply sequencer 3 3 2 Status LEDs Eight status LEDs on the TSW14J57EVM indicate the status of the FPGA DDR4 and JESD204B interface D1 Indicates DAC EVM established SYNC with the TSW14J57 device when off D2 Indicates presence of device c...

Page 8: ...ial programming of ADC and DAC EVMs that support this feature The connector pinout description is shown in Table 4 Table 4 FMC Connector Description of the TSW14J57 FMC Signal Name FMC Pin Standard JESD204 Application Mapping Description RX0_P N C6 and C7 Lane 0 M C JESD Serial data transmitted from mezzanine and received by carrier RX1_P N A2 and A3 Lane 1 M C JESD Serial data transmitted from me...

Page 9: ... mezzanine TX12_P N Z28 and Z29 Lane 12 C M JESD Serial data transmitted from carrier and received by mezzanine TX13_P N Y30 and Y31 Lane 13 C M JESD Serial data transmitted from carrier and received by mezzanine TX14_P N Z8 and Z9 Lane 14 C M JESD Serial data transmitted from carrier and received by mezzanine TX15_P N Y6 and Y7 Lane 15 C M JESD Serial data transmitted from carrier and received by...

Page 10: ... be used for troubleshooting only The board default setup is with the FPGA JTAG pins connected to JTAG connector J3 The FPGA can be programmed using this connector if the MSEL inputs are set to the proper logic levels These are set by solder jumpers SJP1 3 Consult the Intel PSG data sheet for more information regarding JTAG programming The FPGA also has the parallel programming inputs connected to...

Page 11: ...n of the GUI has already been installed make sure to uninstall it before loading a newer version If the GUI detects that a newer version of the GUI is available online http www ti com tool DATACONVERTERPRO SW it will assist the user with downloading the latest version from the TI website The GUI automatically interrogates the product website for latest version every seven days but the latest versi...

Page 12: ...d Data Converter Pro and double click on the executable called High Speed Data Converter Pro exe to start the GUI The GUI first attempts to connect to the EVM USB interface If the GUI identifies a valid board serial number a pop up opens displaying this value as shown in Figure 4 The user can connect several TSW14J57 EVMs to one host PC but the GUI can only connect to one at a time When multiple b...

Page 13: ...selecting Connect to the Board If this still does not correct this issue check the status of the host USB port When the software is installed and the USB cable is connected to the TSW14J57EVM and the PC the TSW14J57 USB 3 0 converter should be located in the Hardware Device Manager under the universal serial bus controllers as shown in Figure 6 labeled as Cypress FX3 USB Streamer Example Device Wh...

Page 14: ...ram Files x86 Texas Instruments High Speed Data Converter Pro 14J57 Details Firmware To load a firmware after the GUI has established connection click the Select ADC window in the top left of the GUI and select the device to evaluate for example ADC34J45_LMF_422 as shown in Figure 7 The GUI prompts the user to update the firmware for the ADC Click Yes The GUI will display the message Downloading F...

Page 15: ...individual EVM User s Guide available on www ti com If the message appears as shown in Figure 9 verify that all jumpers are in the default position and all power status LEDs are illuminated If certain jumpers are not installed in the proper location the USB 3 0 Controller will not boot from flash memory If any power status LED is off there may be a problem with a power supply on the board which ca...

Page 16: ...y set forth above or credit User s account for such EVM TI s liability under this warranty shall be limited to EVMs that are returned during the warranty period to the address designated by TI and that are determined by TI not to conform to such warranty If TI elects to repair or replace such EVM TI shall have a reasonable time to repair such EVM or provide replacements Repaired EVMs shall be warr...

Page 17: ...the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated Antenna types not included in this list having a gain greater than the maximum gain indicated for that type are strictly prohibited for use with this device Concernant les EVMs avec antennes détachables Conformément à la réglementation d Industrie Canada le présent émetteur radio peut fo...

Page 18: ...ed loads Any loads applied outside of the specified output range may also result in unintended and or inaccurate operation and or possible permanent damage to the EVM and or interface electronics Please consult the EVM user guide prior to connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation even ...

Page 19: ...COST OF REMOVAL OR REINSTALLATION ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES RETESTING OUTSIDE COMPUTER TIME LABOR COSTS LOSS OF GOODWILL LOSS OF PROFITS LOSS OF SAVINGS LOSS OF USE LOSS OF DATA OR BUSINESS INTERRUPTION NO CLAIM SUIT OR ACTION SHALL BE BROUGHT AGAINST TI MORE THAN TWELVE 12 MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS OCCURRED 8 2 Specif...

Page 20: ... TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN including but not limited to any patent right copyright mask work right or other intellectual property right relating to any combination machine or process in which TI product...

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