Texas Instruments TSW14J57EVM, User Manual

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Hardware Configuration
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8 SLWU092 – April 2017
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Copyright © 2017, Texas Instruments Incorporated
TSW14J57 JESD204B High-Speed Data Capture and Pattern Generator Card
User's Guide
NOTE: TRIG_OUT_A, TRIG_OUT_B, TRIG_OUT_C SMAs are used to provide a SYNC signal. The
cables of each trigger signal should have equal length to ensure the trigger signal arrives at
the same time for all boards. TRIG_OUT_B and TRIG_OUT_C are multifunctional SMA
connectors. TRIG_OUT_B and TRIG_OUT_C can be used to provide a primary reference
clock or SYSREF signal by making adjustments to the 0
Ω resistors on the signal path.
3.3.3.2 FPGA Mezzanine Card (FMC+) Connector
The TSW14J57 EVM has one connector to allow for the direct plug in of TI JESD204B serial interface
ADC and DAC EVMs. The specifications for this connector are mostly derived from the ANSI/VITA 57.4
FPGA Mezzanine Card (FMC+) Standard. This standard describes the compliance requirements for a low-
overhead protocol bridge between the IO of a mezzanine card and an FPGA processing device on a
carrier card. This specification is being used by FPGA vendors on their development platforms.
The FMC+ connector, J2, provides the interface between the TSW14J57EVM and the ADC or DAC EVM
under test. This 560-pin Samtec high-speed, high-density connector (part number ASP-184329-01) is
suitable for high-speed differential pairs up to 28 Gbps.
In addition to the JESD204B standard signals, several CMOS single-ended signals and LVDS differential
signals are connected between the FMC+ and FPGA. In the future, these signals may allow the HSDC
Pro GUI to control the SPI serial programming of ADC and DAC EVMs that support this feature. The
connector pinout description is shown in
Table 4 .
Table 4. FMC+ Connector Description of the TSW14J57
FMC+ Signal Name FMC+ Pin Standard JESD204
Application Mapping
Description
RX0_P/N C6 and C7 Lane 0± (M → C) JESD Serial data transmitted from mezzanine and received
by carrier
RX1_P/N A2 and A3 Lane 1± (M → C) JESD Serial data transmitted from mezzanine and received
by carrier
RX2_P/N A6 and A7 Lane 2± (M → C) JESD Serial data transmitted from mezzanine and received
by carrier
RX3_P/N A10 and A11 Lane 3± (M → C) JESD Serial data transmitted from mezzanine and received
by carrier
RX4_P/N A14 and A15 Lane 4± (M → C) JESD Serial data transmitted from mezzanine and received
by carrier
RX5_P/N A18 and A19 Lane 5± (M → C) JESD Serial data transmitted from mezzanine and received
by carrier
RX6_P/N B16 and B17 Lane 6± (M → C) JESD Serial data transmitted from mezzanine and received
by carrier
RX7_P/N B12 and B13 Lane 7± (M → C) JESD Serial data transmitted from mezzanine and received
by carrier
RX8_P/N B8 and B9 Lane 8± (M → C) JESD Serial data transmitted from mezzanine and received
by carrier
RX9_P/N B4 and B5 Lane 9± (M
→
C) JESD Serial data transmitted from mezzanine and received
by carrier
RX10_P/N Y10 and Y11 Lane 10± (M → C) JESD Serial data transmitted from mezzanine and received
by carrier
RX11_P/N Z12 and Z13 Lane 11± (M → C) JESD Serial data transmitted from mezzanine and received
by carrier
RX12_P/N Y14 and Y15 Lane 12± (M → C) JESD Serial data transmitted from mezzanine and received
by carrier
RX13_P/N Z16 and Z17 Lane 13± (M → C) JESD Serial data transmitted from mezzanine and received
by carrier
RX14_P/N Y18 and Y19 Lane 14± (M → C) JESD Serial data transmitted from mezzanine and received
by carrier
RX15_P/N Y22 and Y23 Lane 15± (M → C) JESD Serial data transmitted from mezzanine and received
by carrier