background image

www.ti.com

Hardware Configuration

9

SLWU086C – November 2013 – Revised January 2016

Submit Documentation Feedback

Copyright © 2013–2016, Texas Instruments Incorporated

TSW14J56 JESD204B High-Speed Data Capture and Pattern Generator

Card User's Guide

2.3.3.3

JTAG Connectors

The TSW14J56EVM includes three industry-standard JTAG connectors; one that connects to the JTAG
ports of the FPGA, one that connects to the JTAG pins of the Cypress FX3 USB Contoller and the other
that connects to the programming pins of the power monitor/sequencer device. Jumpers on the
TSW14J56EVM allow for the FPGA to be programmed from the JTAG connector or the USB interface.
JTAG connectors J2, J10 and J16 are to be used for troubleshooting only. The board default setup is with
the FPGA JTAG pins connected to JTAG connector J16. The FPGA can be programmed using this
connector if the MSEL inputs are set to the proper logic levels. These are set by solder jumpers SJP14-
18. Consult the Altera data sheet for more information regarding JTAG programming. The FPGA also has
the parallel programming inputs connected to the USB 3.0 controller. With SJP14-18 in teh default
postions, this allows the FPGA to be programmed by the HSDC Pro software GUI. Every time the
TSW14J56EVM is powered-down, the FPGA configuration is removed. The user must program the FPGA
through the GUI after every time the board is powered-up. J2 can be used to program the USB controller
U33. This device is programmed at power-up using the factory pre-programmed flash device U36. JTAG
connector J10 is used to program the TI UCD90120A power monitor/sequencer device. This device is pre-
programmed at the factory and this interface should only be used for troubleshooting.

2.3.3.4

USB I/O Connection

Control of the TSW14J56EVM is through USB 3.0 connector J9. This provides the interface between
HSDC Pro GUI running on a PC Windows™ operating system and the FPGA. For the computer, the
drivers needed to access the USB port are included on the HSDC Pro GUI installation software that can
be downloaded from the web. The drivers are automatically installed during the installation process. On
the TSW14J56EVM, the USB port is used to identify the type and serial number of the EVM under test,
load the desired FPGA configuration file, capture data from ADC EVMs, and send test pattern data to the
DAC EVMs.

Summary of Contents for TSW14J56

Page 1: ...ystem that captures and evaluates data samples from ADC EVMs and generates and sends desired test patterns to DAC EVMs Trademarks Windows is a trademark of Microsoft Corporation 1 Functionality The TS...

Page 2: ...bps 10 routed transceiver channels 32 Gb DDR3 SDRAM split into four independent 512 164 Gb SDRAMs total of 512M samples each Quarter rate DDR3 controllers supporting up to 800 MHz operation 256K 16 bi...

Page 3: ...Dynamically reconfigurable transceiver data rate Operating range from 0 600 to 12 5 Gbps Figure 2 shows a block diagram of the TSW14J56 EVM Figure 2 TSW14J56 EVM Block Diagram 1 1 ADC EVM Data Captur...

Page 4: ...hat are stored inside the on board DDR3 memory To acquire data on a host PC the FPGA reads the data from memory and transmits parallel data to the on board high speed parallel to USB converter 1 2 DAC...

Page 5: ...tion of the jumpers can be found in Table 2 Table 2 Jumper Description of the TSW14J56 Device Component Description Default SJP1 Power enable to general purpose 10 MHz oscillator Y1 1 to 2 SJP19 SJP21...

Page 6: ...D27 On if VCCDDR_1 5 V is within specification D30 On if VTTDDR_0 75 V is within specification D34 On if VAR power is present D33 On if USB_1 2 V is within specification D28 On after FPGA completes c...

Page 7: ...The connector pinout description is shown in Table 4 Table 4 FMC Connector Description of the TSW14J56 FMC Signal Name FMC Pin Standard JESD204 Application Mapping Description RX0_P N C6 and C7 Lane 0...

Page 8: ...ound device clock Used for special FPGA functions such as sampling SYSREF LA01_P N_CC D8 and D9 DEVCLK C M Mezzanine bound device clock Used for low noise conversion clock SYSREF_P N G9 and G10 SYSREF...

Page 9: ...inputs connected to the USB 3 0 controller With SJP14 18 in teh default postions this allows the FPGA to be programmed by the HSDC Pro software GUI Every time the TSW14J56EVM is powered down the FPGA...

Page 10: ...ftware Follow all on screen instructions Accept the license agreements After the installer has finished click Next The GUI executable and associated files reside in the following directory C Program F...

Page 11: ...the Instrument Option tab at the top left of the GUI and selecting Connect to the Board If this still does not correct this issue check the status of the host USB port When the software is installed...

Page 12: ...ly reside in the directory called C Program Files x86 Texas Instruments High Speed Data Converter Pro 14J56revD Details Firmware To load a firmware after the GUI has established connection click the S...

Page 13: ...s Guide available on www ti com If the message appears as shown in Figure 8 verify that all jumpers are in the default position and all power status LEDs are illuminated If certain jumpers are not ins...

Page 14: ...rce in the USB Interface and Drivers section 10 Revision History Changes from A Revision November 2013 to B Revision Page Changed TSW14J56EVM Interfacing with an ADS42JB49EVM image 2 Changed TSW14J56...

Page 15: ...TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD...

Page 16: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments TSW14J56EVM...

Reviews: