SLOS787H – MAY 2012 – REVISED APRIL 2014
6.10.1.3 Direct Command Mode
Table 6-13. Direct Command Mode
Start
Cmd x
(Optional data or command)
Stop
Figure 6-12. Direct Command Example of Sending 0x0F (Reset) Using SPI With SS
The other Direct Command Codes from MCU to TRF7964A IC are described in
.
6.10.1.4 FIFO Operation
The FIFO is a 127-byte register at address 0x1F with byte storage locations 0 to 126. FIFO data is loaded
in a cyclical manner and can be cleared by a reset command (0x0F) (see
showing this Direct
Command).
Associated with the FIFO are two counters and three FIFO status flags. The first counter is a 7-bit FIFO
byte counter (bits B0 to B6 in register 0x1C) that tracks the number of bytes loaded into the FIFO. If the
number of bytes in the FIFO is n, the register value is n (number of bytes in FIFO register). For example, if
8 bytes are in the FIFO, the FIFO counter (Register 0x1C) has the hexadecimal value of 0x08 (binary
value of 00001000).
A second counter (12 bits wide) indicates the number of bytes being transmitted (registers 0x1D and
0x1E) in a data frame. An extension to the transmission-byte counter is a 4-bit broken-byte counter also
provided in register 0x1E (bits B0 to B3). Together these counters make up the TX length value that
determines when the reader generates the EOF byte.
FIFO status flags are as follows:
•
FIFO overflow
(bit B7 of register 0x1C) – indicates that the FIFO has more than 127 bytes loaded
During transmission, the FIFO is checked for an almost-empty condition, and during reception for an
almost-full condition. The maximum number of bytes that can be loaded into the FIFO in a single
sequence is 127 bytes.
NOTE
The number of bytes in a frame, transmitted or received, can be greater than 127 bytes.
32
Detailed Description
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