background image

TRF796xA

MCU

(MSP430 or ARM)

Matching

VDD_X VDD_I/O

TX_OUT

RX_IN 1

RX_IN 2

VSS

VIN

Parallel

or SPI

Supply

2.7 V to 5.5 V

VDD

V

DD

Crystal

13.56 MHz

XIN

Copyright © 2017, Texas Instruments Incorporated

2

TRF7960A

SLOS732G – JUNE 2011 – REVISED MARCH 2020

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TRF7960A

Device Overview

Copyright © 2011–2020, Texas Instruments Incorporated

The built-in programmable auxiliary voltage regulator delivers up to 20 mA to supply an MCU and
additional external circuits within the reader system.

To evaluate the latest products in the TRF79xx product family – TRF7970A and TRF7964A – see the

NFC

Transceiver Booster Pack.

Documentation

,

Tools, Reference Designs, and Software

,

Samples

(1)

For more information, see

Section 9

,

Mechanical Packaging and Orderable Information

.

Device Information

(1)

PART NUMBER

PACKAGE

BODY SIZE

TRF7960ARHB

VQFN (32)

5 mm × 5 mm

1.4

Application Block Diagram

Figure 1-1

shows a typical application block diagram.

Figure 1-1. Application Block Diagram

Summary of Contents for TRF7960A

Page 1: ...mity and vicinity identification systems The reader is configured by selecting the desired protocol in the control registers Direct access to all control registers allows fine tuning of various reader...

Page 2: ...grammable auxiliary voltage regulator delivers up to 20 mA to supply an MCU and additional external circuits within the reader system To evaluate the latest products in the TRF79xx product family TRF7...

Page 3: ...unctional Block Diagram 11 6 2 Power Supplies 11 6 3 Supply Arrangements 12 6 4 Supply Regulator Settings 13 6 5 Power Modes 14 6 6 Receiver Analog Section 17 6 7 Receiver Digital Section 18 6 8 Oscil...

Page 4: ...20 Texas Instruments Incorporated 2 Revision History NOTE Page numbers for previous revisions may differ from page numbers in the current version Changes from May 18 2017 to March 11 2020 Page Removed...

Page 5: ...ess Connectivity Connect more with the industry s broadest wireless connectivity portfolio Products for NFC RFID TI provides one of the industry s most differentiated NFC and RFID product portfolios a...

Page 6: ...ed supply 2 7 V to 5 V normally connected to VDD_PA pin 4 4 VDD_PA INP Supply for PA normally connected externally to VDD_RF pin 3 5 TX_OUT OUT RF output selectable output power 100 mW or 200 mW with...

Page 7: ...O_7 BID I O pin for parallel communication MOSI for serial communication SPI 25 EN2 INP Selection of power down mode If EN2 is connected to VIN then VDD_X is active during power down mode 2 for examp...

Page 8: ...ice 5 Specifications 5 1 Absolute Maximum Ratings 1 over operating free air temperature range unless otherwise noted 2 MIN MAX UNIT Input voltage range VIN 0 3 6 V Maximum current IIN 150 mA Maximum o...

Page 9: ...y current without antenna driver current Oscillator regulators RX and AGC are active TX is off 10 5 14 mA ION2 Supply current in TX half power Oscillator regulators RX AGC and TX active POUT 100 mW 70...

Page 10: ...depends on the capacitive load Maximum SPI clock speed should not exceed 10 MHz This clock speed is acceptable only when external capacitive load is less than 30 pF MISO driver has a typical output r...

Page 11: ...Description Copyright 2011 2020 Texas Instruments Incorporated 6 Detailed Description 6 1 Functional Block Diagram Figure 6 1 shows the functional block diagram Figure 6 1 Functional Block Diagram 6 2...

Page 12: ...used per reference schematics When configured for 3 V manual operation the VDD_A output can be set from 2 7 V to 3 4 V in 100 mV steps see Table 6 2 NOTE The configuration of VDD_A and VDD_X regulator...

Page 13: ...s VSS pin 10 the analog negative supply is VSS_A pin 15 the logic negative supply is VSS_D pin 29 the RF output stage negative supply is VSS_PA pin 6 and the negative supply for the RF receiver VSS_RX...

Page 14: ...0 0 0 VDD_RF 2 7 V VDD_A 2 7 V VDD_X 2 7 V The regulator configuration function adjusts the regulator outputs by default to 250 mV below VIN level but not higher than 5 V for VDD_RF 3 4 V for VDD_A an...

Page 15: ...Mode 4 full power 5 VDC x 1 21 07 On On On x On 130 23 20 to 25 s Mode 4 full power 3 3 VDC x 1 20 07 On On On x On 67 18 Mode 3 half power 5 VDC x 1 31 07 On On On x On 70 20 20 to 25 s Mode 3 half p...

Page 16: ...the reader stays active If the EN input is not set high EN 0 within 100 s after the SYS_CLK output is switched from auxiliary clock 60 kHz to high frequency clock derived from the crystal oscillator...

Page 17: ...default MUX setting is RX_IN1 connected to the main receiver and RX_IN2 connected to the auxiliary receiver To determine the signal quality the response from the tag is detected by the main pin RX_IN...

Page 18: ...process special signals such as the start of frame SOF end of frame EOF start of communication and end of communication are automatically removed The parity bits and CRC bytes are also checked and re...

Page 19: ...the start of tag response If there is no tag response in the defined time an interrupt request is sent and a flag is set in the IRQ Status register 0x0C This enables the external controller to be rel...

Page 20: ...e communication to the Tag this means the TX must be on Bit 1 in the Chip Status Control register 0x00 defines if internal RSSI or the external RSSI value is stored in the RSSI Levels and Oscillator S...

Page 21: ...rolled by the Chip Status Control register 0x00 and the EN and EN2 signals The oscillator generates the RF frequency for the RF output stage and the clock source for the digital section The buffered c...

Page 22: ...he modulation type ASK or OOK at pin 12 External control of the modulation type is made possible only if enabled by setting B6 in the Modulator and SYS_CLK Control register 0x09 to 1 In normal operati...

Page 23: ...43 B protocol ISO14443A High Bit Rate and Parity Options register 0x03 This register enables the use of different bit rates for RX and TX operations in ISO IEC 14443 high bit rate protocol Besides tha...

Page 24: ...he master device The MCU initiates all communications with the TRF7960A The TRF7960A makes use of the Interrupt Request IRQ pin in both parallel and SPI modes to prompt the MCU for servicing attention...

Page 25: ...ional data the address is incremented by one Continuous mode can be used to write to a block of control registers in a single stream without changing the address for example setup of the predefined st...

Page 26: ...the format of a continuous address register read and Figure 6 5 and Figure 6 6 show examples Table 6 8 Continuous Address Mode Start Adr x Data x Data x 1 Data x 2 Data x 3 Data x 4 Data x n StopCont...

Page 27: ...Table 6 9 lists the format of a single address register read and Figure 6 7 and Figure 6 8 show examples Table 6 9 Noncontinuous Address Mode Single Address Mode Start Adr x Data x Adr y Data y Adr z...

Page 28: ...keeps track of the number of bytes loaded into the FIFO If the number of bytes in the FIFO is n the register value is n 1 number of bytes in FIFO register If 8 bytes are in the FIFO the FIFO counter b...

Page 29: ...ata or remove the data as necessary The MCU also checks the number of data bytes to be sent so as to not surpass the value defined in TX length bytes The MCU also signals the transmit logic when the l...

Page 30: ...he MCU at the end of the receive operation if the receive data string was shorter than or equal to 8 bytes The MCU receives the interrupt request then checks to determine the reason for the interrupt...

Page 31: ...ta to the FIFO if needed At the end of the transmit operation an interrupt is sent to inform the MCU that the task is complete 6 12 6 Serial Interface Communication SPI When an SPI interface is used I...

Page 32: ...Read Figure 6 15 Dummy Read Using SPI With SS 6 12 6 1 Serial Interface Mode Without Slave Select SS The serial interface without the slave select pin must use delimiters for the start and stop condit...

Page 33: ...irst Figure 6 17 SPI With Slave Select Timing The read command is sent out on the MOSI pin MSB first in the first eight clock cycles MOSI data changes on the falling edge and is validated in the reade...

Page 34: ...lt operation Full sequences for other settings and protocols can be downloaded from http www ti com lit zip sloc240 Figure 6 20 Inventory Command Sent From MCU to TRF7960A The TRF7960A reads these byt...

Page 35: ...TX is complete This is followed by dummy clock and reset of FIFO with dummy clock Then if a tag is in the field and no error is detected by the reader a second interrupt is expected and occurs in this...

Page 36: ...byte is 0x00 for no error The next byte is the DSFID usually shipped by manufacturer as 0x00 then the UID shown here up to the next most significant byte MSByte the MFG code 0x07 to indicate TI silico...

Page 37: ...ght 2011 2020 Texas Instruments Incorporated Figure 6 24 IRQ With One Byte in FIFO TI recommends resetting the FIFO after receiving data Additionally the RSSI value of the tag can be read out at this...

Page 38: ...control over the RF modulation through the MOD input This mode is provided so that the application can implement a protocol that has the same bit coding as one of the protocols implemented in the read...

Page 39: ...ion 0x20 for 6 78 MHz clock and ASK 10 modulation 0x22 for 6 78 MHz clock and ASK 7 modulation 0x23 for 6 78 MHz clock and ASK 8 5 modulation 0x24 for 6 78 MHz clock and ASK 13 modulation 0x25 for 6 7...

Page 40: ...r the RF modulation through the MOD input Figure 6 28 Control of RF Modulation Using MOD The microcontroller is responsible for generating data according to the coding specified by the particular stan...

Page 41: ...cription Copyright 2011 2020 Texas Instruments Incorporated Figure 6 29 Receive Data Bits and Framing Level ISO IEC 14443 A Step 7 Exit direct mode 0 When an EOF is received data transmission is over...

Page 42: ...values from Table 6 11 are substituted in Table 6 12 Bits 0 to 4 Also the most significant bit MSB in Table 6 12 must be set to 1 Table 6 12 Address Command Word Bit Distribution BIT DESCRIPTION BIT F...

Page 43: ...ceiver command puts the digital part of receiver bit decoder and framer in reset mode This is useful in an extremely noisy environment where the noise level could otherwise cause a constant switching...

Page 44: ...ltage in the RF_IN1 input and RSSI code respectively NOTE If the command is executed immediately after power up and before any communication with tag was performed the command must be preceded by the...

Page 45: ...2 0x04 TX Timer Setting H byte R W Section 6 14 1 2 3 0x05 TX Timer Setting L byte R W Section 6 14 1 2 4 0x06 TX Pulse Length Control R W Section 6 14 1 2 5 0x07 RX No Response Wait R W Section 6 14...

Page 46: ...ides user direct access to AFE direct mode 0 or lets the user add custom framing direct mode 1 Bit 6 of the ISO Control register must be set before entering direct mode 0 or 1 0 ISO mode default Uses...

Page 47: ...be made in register 0x02 or 0x03 Table 6 18 ISO Control Register ISO_4 to ISO_0 iso_4 iso_3 iso_2 iso_1 iso_0 PROTOCOL REMARKS 0 0 0 0 0 ISO IEC 15693 low bit rate 6 62 kbps one subcarrier 1 out of 4...

Page 48: ...SOF 1 length 02 etu B2 sof_l0 1 SOF 0 length 11 etu 0 SOF 0 length 10 etu B1 l_egt 1 EGT after each byte 0 EGT after last byte is omitted B0 Unused 6 14 1 2 2 ISO14443A High Bit Rate and Parity Option...

Page 49: ...imer length MSB See Table 6 22 for timer length description B4 tm_lengthC Timer length B3 tm_lengthB Timer length B2 tm_lengthA Timer length B1 tm_length9 Timer length B0 tm_length8 Timer length LSB 6...

Page 50: ...at 212 kbps 737 ns for ISO IEC 14443 A at 424 kbps 442 ns for ISO IEC 14443 A at 848 kbps pulse length control disabled B6 Pul_p1 B5 Pul_p0 B4 Pul_c4 B3 Pul_c3 B2 Pul_c2 B1 Pul_c1 B0 Pul_c0 6 14 1 2...

Page 51: ...t operation in which the receive decoders are not active held in reset state This prevents incorrect detections resulting from transients following the transmit operation The value of the RX wait time...

Page 52: ...OOK or ASK using the OOK pin is only possible if the function is enabled by setting B6 1 en_ook_p in this register 0x09 and the ISO Control register 0x01 B6 1 When configured this way the MOD pin pin...

Page 53: ...UNCTION DESCRIPTION B7 C212 Band pass 110 kHz to 570 kHz Appropriate for 212 kHz subcarrier system FeliCa B6 C424 Band pass 200 kHz to 900 kHz B5 M848 Band pass 450 kHz to 1 5 MHz Appropriate for Manc...

Page 54: ...pin becomes modulation output for external TX amplifier B5 io_low 1 Enable low peripheral communication voltage When B5 1 maintains the output driving capabilities of the I O pins connected to the le...

Page 55: ...V VDD_A 2 9 V VDD_X 2 9 V 0B 0 0 0 1 VDD_RF 2 8 V VDD_A 2 8 V VDD_X 2 8 V 0B 0 0 0 0 VDD_RF 2 7 V VDD_A 2 7 V VDD_X 2 7 V 1 x don t care Table 6 31 Supply Regulator Setting Automatic 5 V System REGIS...

Page 56: ...nd of TX Signals that TX is in progress The flag is set at the start of TX but the interrupt request IRQ 1 is sent when TX is finished B6 Irg_srx IRQ set due to RX start Signals that RX SOF was receiv...

Page 57: ...pt enable for FIFO Default 1 B4 En_irq_err1 Interrupt enable for CRC Default 1 B3 En_irq_err2 Interrupt enable for Parity Default 1 B2 En_irq_err3 Interrupt enable for Framing error or EOF Default 1 B...

Page 58: ...reader so the new tag response level can be measured Section 6 7 1 1 and Section 6 7 1 2 describe the RSSI levels calculated to RF_IN1 and RF_IN2 The RSSI has 7 steps 3 bits with 4 dB increment The in...

Page 59: ...output selection 0 First stage output used for analog out and digitizing 1 Second stage output used for analog out and digitizing B3 low2 Second stage gain 6 dB HP corner frequency 2 B2 low1 First sta...

Page 60: ...Fb3 FIFO bytes fb 3 Bits B0 B3 indicate how many bytes that are loaded in FIFO were not read out yet displays N 1 number of bytes If 8 bytes are in the FIFO this number is 7 also see register 0x0C bi...

Page 61: ...nd EN 0 The register is also automatically reset at TX EOF Table 6 41 TX Length Byte2 Register 0x1E BIT NO BIT NAME FUNCTION DESCRIPTION B7 Txl3 Number of complete byte bn 3 Low nibble of complete int...

Page 62: ...are essential to avoid interference The recommended clock frequency on the DATA_CLK line is 2 MHz This schematic shows matching to a 50 port which allows connection to a properly matched 50 antenna c...

Page 63: ...s Avoid crossing of digital lines under RF signal lines Also avoid crossing of digital lines with other digital lines whenever possible If the crossings are unavoidable 90 crossings should be used to...

Page 64: ...mpedance Matching Smith Chart Resulting power out can be measured with a power meter spectrum analyzer with power meter function or other equipment capable of making a hot measurement Take care to obs...

Page 65: ...ly qualified production devices with no prefix Device development evolutionary flow xTRF Experimental device that is not necessarily representative of the electrical specifications of the final device...

Page 66: ...entire system current draw over time is of the utmost concern TRF7960A RFID Multiplexer Example System This application report describes the 16 channel high frequency HF 13 56 MHz RFID reader system...

Page 67: ...tric changes could cause the device not to meet its published specifications 8 8 Export Control Notice Recipient agrees to not knowingly export or re export directly or indirectly any product or techn...

Page 68: ...exas Instruments Incorporated 9 Mechanical Packaging and Orderable Information The following pages include mechanical packaging and orderable information This information is the most current data avai...

Page 69: ...000ppm threshold Antimony trioxide based flame retardants must also meet the 1000ppm threshold requirement 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standar...

Page 70: ...PACKAGE OPTION ADDENDUM www ti com 10 Dec 2020 Addendum Page 2...

Page 71: ...Pins SPQ Reel Diameter mm Reel Width W1 mm A0 mm B0 mm K0 mm P1 mm W mm Pin1 Quadrant TRF7960ARHBR VQFN RHB 32 3000 330 0 12 4 5 3 5 3 1 5 8 0 12 0 Q2 TRF7960ARHBT VQFN RHB 32 250 180 0 12 4 5 3 5 3 1...

Page 72: ...Package Type Package Drawing Pins SPQ Length mm Width mm Height mm TRF7960ARHBR VQFN RHB 32 3000 853 0 449 0 35 0 TRF7960ARHBT VQFN RHB 32 250 210 0 185 0 35 0 PACKAGE MATERIALS INFORMATION www ti com...

Page 73: ...IEW Images above are just a representation of the package family actual package may vary Refer to the product data sheet for package details VQFN 1 mm max height RHB 32 PLASTIC QUAD FLATPACK NO LEAD 5...

Page 74: ...2 25 OPTIONAL PIN 1 ID 0 1 C A B 0 05 C EXPOSED THERMAL PAD 33 SYMM SYMM NOTES 1 All linear dimensions are in millimeters Any dimensions in parenthesis are for reference only Dimensioning and toleranc...

Page 75: ...age is designed to be soldered to a thermal pad on the board For more information see Texas Instruments literature number SLUA271 www ti com lit slua271 5 Vias are optional depending on application re...

Page 76: ...4223442 B 08 2019 NOTES continued 6 Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release IPC 7525 may have alternate design recommendations 33 SYMM METAL...

Page 77: ...e resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reprod...

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