Texas Instruments TRF3701 User Manual Download Page 27 | Manualshive

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5-1

Schematics

Schematics

This chapter shows the EVM schematic.

Chapter 5

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Summary of Contents for TRF3701

Page 1: ...TRF3701 TRF3702 Quadrature Modulator Evaluation Module 2004 Wireless Infrastructure Products User s Guide SLWU007...

Page 2: ...ute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual pro...

Page 3: ...handling or use of the goods Please be aware that the products received may not be regulatory compliant or agency certified FCC UL CE etc Due to the open construction of the product it is the user s r...

Page 4: ...ere is uncertainty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 60 C The EVM is designe...

Page 5: ...hapter 1 Overview Chapter 2 Physical Description Chapter 3 Circuit Description Chapter 4 Circuit Board Test Points Chapter 5 Schematic Information About Cautions and Warnings This book may contain cau...

Page 6: ...uency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules which are designed to provide reasonable protection against radio...

Page 7: ...2 1 PCB Layout 2 2 2 2 Parts List 2 5 3 Circuit Description 3 1 3 1 Circuit Function 3 2 3 1 1 Differential Single Ended Inputs via Buffer Amplifiers 3 2 3 1 2 Differential Singled Ended Inputs Withou...

Page 8: ...3 Power Plane 2 3 2 4 Bottom Layer 2 4 4 1 Silkscreen Top Layer Test Points Location 4 2 4 2 Bottom Layer Test Points Location 4 3 Tables 1 1 EVM Configuration 1 3 2 1 Parts List 2 5 3 1 Power Supply...

Page 9: ...or up conversion of signals from the transmit chain DAC to the RF power amplifier device Evaluating a modulator complex performance involves careful bias voltage setup an LO signal and at least two si...

Page 10: ...I respectively The Q signals are connected to J5 Q and J11 Q respectively The LO signal is fed to J2 and the SMA connector J3 is used to monitor the output signal from the quadrature modulator U1 The...

Page 11: ...with 0 C53 C55 R30 R32 if 50 termination required Apply dc offset VCM 3 7 Vdc to J6 and adjust R33 and R34 to optimize the dc offset level of the complementary I Q inputs Apply I signal to J9 Q to J12...

Page 12: ...zer to the SMA connector marked RFOUT J3 and monitor the TRF3701 TRF3702 output 6 To optimize the carrier suppression this modulator performs the following if using on board dc offset through J3 a Con...

Page 13: ...escription Physical Description This chapter discusses the four layer PCB layout component placement and list of components used on the evaluation module Topic Page 2 1 PCB Layout 2 2 2 2 Parts Llists...

Page 14: ...CB Layout 2 2 2 1 PCB Layout The EVM is constructed on a four layer 76 mm x 76 mm x 1 575 mm thick PCB using FR 4 material Figure 2 1 through Figure 2 4 show the individual layers Figure 2 1 Top Layer...

Page 15: ...PCB Layout 2 3 Physical Description Figure 2 2 Layer 2 Ground Plane...

Page 16: ...PCB Layout 2 4 Figure 2 3 Layer 3 Power Plane...

Page 17: ...PCB Layout 2 5 Physical Description Figure 2 4 Bottom Layer...

Page 18: ...RJ 6ENF402R0V Panasonic R6 R7 56 2 resistor 1 16 W 1 1210 4 ERJ 13NF56R2 Panasonic R1 R3 R16 1 k resistor 1 16 W 1 603 4 ERJ 3EKF1 00K Panasonic R23 R26 49 9 resistor 1 16 W 1 603 0 ERJ 3EKF49R9V Pana...

Page 19: ...3 1 Circuit Description Circuit Description This chapter discusses the various functions of the EVM Topic Page 3 1 Circuit Function 3 2 Chapter 3...

Page 20: ...ver the EVM is configured to accept the single ended I channel signal on J4 The Q channel input is via J5 3 1 2 Differential Singled Ended Inputs Without Buffer Amplifier Direct I Q inputs without the...

Page 21: ...nectors J6 and J13 are used to supply the dc bias voltage to U1 I Q input channels Both connectors are a 3 position male Molex header part number 8610903 Table 3 2 CM Bias Voltage J6 Pin Description 1...

Page 22: ...3 4...

Page 23: ...4 1 Circuit Board Test Points Circuit Board Test Points This chapter shows the circuit board test points Topic Page 4 1 Circuit Board Test Point Locations 4 2 Chapter 4...

Page 24: ...ocations When a quick indication of the dc bias level and ac signal level on the I Q inputs is required simply probe the appropriate test points in Figure 4 1 and Figure 4 2 Figure 4 1 Silkscreen Top...

Page 25: ...Point Locations 4 3 Circuit Board Test Points Figure 4 2 Bottom Layer Test Points Location J11 J5 J8 J4 J2 J3 E6 E5 E4 E3 J1 J7 J9 J13 J12 J6 R29 R34 R33 QREF ADJ IREF ADJ R20 R13 J10 R22 R21 R14 R15...

Page 26: ...4 4...

Page 27: ...5 1 Schematics Schematics This chapter shows the EVM schematic Chapter 5...

Page 28: ...TERMINED BY MATCHING IF NOT USING MATCHING MAKE L1 A 0 OHM RESISTOR LEAVE C22 AND C52 UNPOPULATED 2 OPTIONAL USED TO TIE IREF QREF TOGETHER Note 3 Note 3 7VA FB1 C1 10uF C33 1uF C38 0 01uF C43 47 uF 7...

Page 29: ...402 7VA C17 1uF C28 01uF C32 10pF R15 22 1 R11 392 QVIN QVIN R14 22 1 QVIN QVIN C15 1uF C26 01uF VCOM2 VCOM2 C16 1uF C27 01uF 7VA C31 10pF R10 392 TRF3701 02 P MILLER Y DEWONCK 2 2 A R17 374 1 2 3 4 5...

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