EVM Details
8
SLVUBT0 – December 2019
Copyright © 2019, Texas Instruments Incorporated
TPS6594x-Q1 Evaluation Module
NOTE:
The PMIC device can be configured for a power good level of 3.3 V or 5.0 V for the VCCA
pin. Align the USB_3V3/VSYS/VBUS jumper with the PMIC configuration. The default PMIC
configuration is 3.3 V.
3.4
Signal Headers
Signal headers are provided for the LDOs, BUCK regulators, and GPIO signals. Headers J13 (LDOs), J12
(BUCKs), and J11 (GPIOs) are placed on the perimeter of the board to enable probing of these signals
even when in a stacked configuration.
There are 6 signal headers associated with the LDO; five are shown in the EVM silk screen capture,
. These include J20 and J21, the power inputs to the LDOs, J14 and J13 , the LDO outputs, and
J18 and J19 which can be used to measure Power Supply Rejection Ratio (PSRR) on LDO3 and LDO4.
All pins of J20 are connected to the VCCA, and J20 is placed next to J21 to easily connect all the LDO
power inputs to the VCCA; this is the default jumper configuration. An external power supply for the LDOs
can also be applied directly to J21.
Figure 3. LDO Headers
NOTE:
J13 and J14 provide the same LDO outputs; however, J13 should only be used for probing.
J14 provides a shorter and wider trace, lowering the impedance and supporting maximum
loads of 500 mA. Also, pin 7 is a different signal for J13 and J14; GND_S and AMUXOUT,
respectively.
Signal Header J12 provides access to all of the buck regulator outputs, GND_S and VCCA_S.
NOTE:
Header J12 should only be used for voltage probing and not for power delivery.
GPIO signals are provided on both J9 and J11. J8 (PU) is located directly above J9 enabling each GPIO
to be pulled to the voltage defined in table x through a 10 k
Ω
resistor pullup. J10 (PD) is located directly
below J9 to enable shorting each GPIO directly to GND.
