Texas Instruments TPS6593EVM, User Manual

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3.3 Test Point Descriptions
Numerous test points are provided to access voltages and signals. All test points are designed for sensing
voltages only and are not designed to carry large DC currents.
Table 3-3. Test Point Descriptions
Test Point Device Pin Description
TP1 VCCA This point can be used to measure IDDQ, when resistor R58 is removed.
TP2 VIO_IN This point can be used to measure IDDQ when resistor R65 is removed.
TP3, TP4, TP5 GND NA
TP6 FB_B3 External voltage monitor connection.
TP7 FB_B4
TP8 GPIO10 (SYNCCLKIN) Sync Clock input, up to 4.4 Mhz
TP9 SW_B1 Test Point for the switch node. Not populated to reduce EMI.
TP10 SW_B2
TP11 SW_B3
TP12 SW_B4
TP13 SW_B5
TP14 GND NA
3.4 Configuration Headers
There are six headers available to configure the EVM function. Headers J26 and J37 configure the backup
power supply and master and slave mode of operation respectively. J45 is connected to J37, which can pull the
nPWRON/ENABLE pin of the PMIC to a logic high or low. Header J7, as shown in the silk screen picture in
Figure 3-1 and Figure 3-2 , is used to configure the EVM to match the feature setting written to the device
configuration registers. J30 is used to select the PMIC IO voltage, either 1.8 V or 3.3 V. The sixth header is a
portion of J15, which allows VSYS to be powered from the USB connection and the configuration of GPIO1.
Figure 3-1. TPS6594EVM Header J7
www.ti.com EVM Details
SLVUBT0A – JUNE 2020 – REVISED JANUARY 2021
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TPS6594x-Q1 Evaluation Module 7
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