Texas Instruments TPS65235-1, User Manual

Page: 7 / 19

www.ti.com
Bench Test Setup Conditions
7 SLVUAZ0 – November 2016
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Evaluation Module for the TPS65235-1 LNB Voltage Regulator With I
2
C
Interface for DiSEqC2.x Application
Table 1. Input and Output Connection
# Function Description
J1 VOUT Connector VLNB output
J2 Vin Connector Apply power supply through this connector
Table 2. Jumpers and Switches
# Function Placement Comment
J3
Output voltage control (SCL)
If the IC is not controlled by I
2
C, VCTRL pin and SCL pin
are combined to control the VLNB output voltage. Refer
to
Table 3 .
Jumper J3-2 and J3-1 makes SCL to VCC connection
and gives VLNB with output 14.6 V or 19.4 V.
Jumper J3-2 and J3-3 makes SCL to GND connection
and gives VLNB with output 13.4 V or 18.2 V.
I
2
C Power
If the IC is controlled by I
2
C, this is used to provide the
I
2
C power which is connected to the SCL and SDA
through pull-up resistors.
Leaving non jumper connected sets the power to be 3.3
V from the I
2
C interface adapter.
Shorting the J3-1 and J3-2 by jumper sets the power to
be VCC.
On board VCC is 6.3 V
J4 Tone control (EXTM)
Toggle the EXTM signal (J4-2 to J4-3 and then J4-2 to
J4-1), the internal tone signal is superimposed at the
VLNB output VOUT.
EXTM to GND (J4-2 to J4-3), no internal tone signal is
superimposed at the VOUT.
J5 Output voltage control (VCTRL)
If the IC is not controlled by I
2
C, VCTRL pin and SCL pin
are combined to control the VLNB output voltage. Refer
to
Table 3 .
Jumper J5-2 and J5-1 makes VCTRL to VCC connection
and gives VLNB with output 18.2 V or 19.4 V.
Jumper J5-2 and J5-3 makes VCTRL to VCC connection
and gives VLNB with output 13.4 V or 14.6 V.
J6 I
2
C address set (ADDR)
This pin is the I
2
C address set pin: tie to VCC sets I
2
C
address with 0x08H; floating sets I
2
C address with
0x09H; tie to GND sets I
2
C address with 0x10H; Resistor
divider R9A and R9B make ADDR pin at the voltage to
set the I
2
C address with 0x11H. Refer to Table 4 .
With 3 V-> VCC- 0.8 V will
set the I
2
C address 0x11H
J7 VLNB output enable (EN)
Jumper EN to GND disables the VLNB output (short J7-2
to J7-3).
Jumper EN to Vin through a 100-k
Ω resistor enables the
VLNB output (short J7-2 to J7-1).
Leaving J7 open also enables VLNB output.
Table 3. VLNB Output Control Without I
2
C Interface
Connection
EN SCL VCRTL VLNB
H H H 19.4 V
H H L 14.6 V
H L H 18.2 V
H L L 13.4 V
L X X 0 V