background image

Figure 6-5. TPS6503xx-Q1 GUI Block Diagram Page

6.2.3 Registers

The Registers section provides an overview of the internal register map, and includes basic interfaces for each
PMIC register

Figure 6-6

 illustrates the register page and the primary interactive regions.

Manually 

enter hex 

value

(Optional)

Select 

autoread 

interval

Read 

selected 

register

Read all 

registers

Select I2C 

Write 

Behavior

Register 

Field 

Information

Register 

Information

Select 

register field 

value

Figure 6-6. Register Page Interfaces

The register table displays each register name, address, last known value from the PMIC, and corresponding bit
values. Selecting a title or bit fields in the table will update the Field View column on the right side of the GUI.
The Field View displays the individual fields contained within the associated register address. Within the register
page, clicking a blue icon containing a question mark (?) will expand additional descriptions if available. The
expanded description views can then be closed by clicking the red (x) icon.

This register page can poll the device periodically using the 

Auto Read

 feature in the top right corner, or allow

manual read instructions using the 

Read Register

 and 

Read All Registers

 buttons.

Graphical User Interface

www.ti.com

12

TPS650330-Q1 EVM User's Guide

SLVUBI2A – JULY 2018 – REVISED OCTOBER 2020

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Copyright © 2020 Texas Instruments Incorporated

Summary of Contents for TPS6503-Q1 Series

Page 1: ...Screen 11 Figure 6 5 TPS6503xx Q1 GUI Block Diagram Page 12 Figure 6 6 Register Page Interfaces 12 Figure 6 7 TPS6503xx Q1 GUI Device Configuration Page 13 Figure 6 8 Device Selection for Generating...

Page 2: ...Table 5 1 TPS650330 Q1 EVM Test Points 7 Table 10 1 TPS650330 Q1 EVM Bill of Materials 29 Table 11 1 TPS65033x Q1 Silicon Revision B0 Feature Changes 32 Trademarks Google Chrome is a trademark of Goo...

Page 3: ...to enable the Buck 1 and Buck 2 regulators 6 Set GPIO switch S4 to ON to enable the Buck 3 and LDO regulators 7 Load the Camera PMIC GUI and ensure the adapter has been recognized by the PC If the GU...

Page 4: ...o 350 mV Table 3 6 Mid Vin Buck1 Configurable Settings Feature Configurable Range Output Voltage 2 5 V to 4 0 V PVIN_B1 UVLO Rising 3 64 V to 9 36 V PVIN_B1 UVLO Falling 3 5 V to 9 V Output Discharge...

Page 5: ...il Default Pin 4 PMIC LDO Input Supply Rail Pin 5 Buck2 Output Rail Pin 6 PMIC LDO Input Supply Rail Pin 7 Buck3 Output Rail Pin 8 PMIC LDO Input Supply Rail 3 2 7 Low Noise LDO Features Table 3 12 Lo...

Page 6: ...t Supply Rail Pin 7 PMIC LDO Output Rail Pin 8 VIO Input Supply Rail Pin 9 Dedicated 3 3 V LDO Pin 10 VIO Input Supply Rail 4 EVM Configurations The following sections outline how to configure the TPS...

Page 7: ...CL TP2 VREG TP3 GPIO TP4 Buck 1 Output TP5 VBUS TP6 SDA TP7 V1P8_INT TP8 nINT TP9 PMIC LDO Input TP10 SEQ TP11 nRSTOUT TP12 Buck 2 Output TP13 Buck 2 Input TP14 VIO TP15 Buck 3 Output TP16 Buck 3 Inpu...

Page 8: ...e GUI requires both a browser plugin and the TI Cloud Agent software for access to the local USB ports The GUI can also be downloaded for offline operation by hovering over the downward arrow in the G...

Page 9: ...650330 Q1 EVM Debugging Flow Chart www ti com Graphical User Interface SLVUBI2A JULY 2018 REVISED OCTOBER 2020 Submit Document Feedback TPS650330 Q1 EVM User s Guide 9 Copyright 2020 Texas Instruments...

Page 10: ...EVM on board MCU is showing up under the Device Manager with a Stellaris title the MCU firmware needs to be updated to communicate with the GUI One way to do this is with TI s free LM Flash Programmer...

Page 11: ...ng four sections through the tiles on the bottom of the page Figure 6 4 TPS6503xx Q1 GUI Home Screen 6 2 2 Block Diagram The Block Diagram section displays the typical components and functional blocks...

Page 12: ...responding bit values Selecting a title or bit fields in the table will update the Field View column on the right side of the GUI The Field View displays the individual fields contained within the ass...

Page 13: ...atures that can prevent I2C writes to various registers within the device The status of these locks will always be displayed in the top right hand corner of the Device Configurations page and can be t...

Page 14: ...he top left corner of the GUI This exports the register settings in a JSON file that is provided to generate the NVM spin Figure 6 9 Example Settings Output 6 2 4 2 Configuring the Power Sequence The...

Page 15: ...ased on the sequence settings present when the UPDATE TIMING DIAGRAM button is clicked As noted rise and fall times are approximate and the maximum sequence length is 200 ms Changes to regulator enabl...

Page 16: ...the existing register configurations permanently and the PMIC will automatically restart with the latest settings The device can be re programmed multiple times to evaluate various configurations Figu...

Page 17: ...and Buck 2 regulators are enabled allowing the 3 3 V and 1 8 V rails to power up a In a typical camera application this may be sufficient to power up the serializer and enable PMIC programming over t...

Page 18: ...OUT 1 mA to 750 mA in 1 s Figure 7 3 Buck 1 Load Transient VIN 3 3 V VOUT 1 8 V IOUT 1 mA to 300 mA in 1 s Figure 7 4 Buck 2 Load Transient VIN 3 3 V VOUT 1 2 V IOUT 1 mA to 300 mA in 1 s Figure 7 5 B...

Page 19: ...tput Voltage Ripple VIN 3 3 V VOUT 1 2 V IOUT 600 mA Figure 7 8 Buck 3 Output Voltage Ripple 7 4 Efficiency Plots VIN 9 V VOUT 3 3 V Ta 25 C Figure 7 9 Buck 1 Efficiency Curve www ti com Typical Perfo...

Page 20: ...5 C Figure 7 11 Buck 3 Efficiency Curve 7 5 LDO Output Noise VIN 3 3 V VOUT 2 8 V IOUT 300 mA Figure 7 12 LDO Output Noise Density Typical Performance Plots www ti com 20 TPS650330 Q1 EVM User s Guide...

Page 21: ...ematic Figure 8 1 TPS650330 Q1 Schematic www ti com TPS650330 Q1 EVM Schematic SLVUBI2A JULY 2018 REVISED OCTOBER 2020 Submit Document Feedback TPS650330 Q1 EVM User s Guide 21 Copyright 2020 Texas In...

Page 22: ...8 2 MSP432E401Y Schematic TPS650330 Q1 EVM Schematic www ti com 22 TPS650330 Q1 EVM User s Guide SLVUBI2A JULY 2018 REVISED OCTOBER 2020 Submit Document Feedback Copyright 2020 Texas Instruments Incor...

Page 23: ...M PCB Layers Figure 9 1 Top Layer www ti com TPS650330 Q1 EVM PCB Layers SLVUBI2A JULY 2018 REVISED OCTOBER 2020 Submit Document Feedback TPS650330 Q1 EVM User s Guide 23 Copyright 2020 Texas Instrume...

Page 24: ...ure 9 2 Mid Layer 1 TPS650330 Q1 EVM PCB Layers www ti com 24 TPS650330 Q1 EVM User s Guide SLVUBI2A JULY 2018 REVISED OCTOBER 2020 Submit Document Feedback Copyright 2020 Texas Instruments Incorporat...

Page 25: ...ure 9 3 Mid Layer 2 www ti com TPS650330 Q1 EVM PCB Layers SLVUBI2A JULY 2018 REVISED OCTOBER 2020 Submit Document Feedback TPS650330 Q1 EVM User s Guide 25 Copyright 2020 Texas Instruments Incorporat...

Page 26: ...ure 9 4 Mid Layer 3 TPS650330 Q1 EVM PCB Layers www ti com 26 TPS650330 Q1 EVM User s Guide SLVUBI2A JULY 2018 REVISED OCTOBER 2020 Submit Document Feedback Copyright 2020 Texas Instruments Incorporat...

Page 27: ...ure 9 5 Mid Layer 4 www ti com TPS650330 Q1 EVM PCB Layers SLVUBI2A JULY 2018 REVISED OCTOBER 2020 Submit Document Feedback TPS650330 Q1 EVM User s Guide 27 Copyright 2020 Texas Instruments Incorporat...

Page 28: ...6 Bottom Layer Mirrored TPS650330 Q1 EVM PCB Layers www ti com 28 TPS650330 Q1 EVM User s Guide SLVUBI2A JULY 2018 REVISED OCTOBER 2020 Submit Document Feedback Copyright 2020 Texas Instruments Incor...

Page 29: ...2 pF 50 V 5 C0G NP0 AEC Q200 Grade 1 0402 0402 GCM1555C1H120JA1 6J MuRata C20 C21 C22 C23 C24 C29 C30 7 0 1 F CAP CERM 0 1 F 25 V 10 X7R 0402 0402 GRM155R71E104KE1 4D MuRata C27 1 2 2 F CAP CERM 2 2 F...

Page 30: ...0 063 W AEC Q200 Grade 0 0402 0402 CRCW04021M00JNED Vishay Dale R3 1 4 87 k RES 4 87 k 1 0 063 W AEC Q200 Grade 0 0402 0402 CRCW04024K87FKED Vishay Dale R4 R7 R8 3 10 k RES 10 k 5 0 063 W AEC Q200 Gr...

Page 31: ...USB ESD Solution with Power Clamp 4 Channels 40 to 85 C 6 pin SON DRY Green RoHS no Sb Br DRY0006A TPD4S012DRYR Texas Instruments U4 1 Single Output Fast Transient Response LDO 1 5 A Adjustable 1 21...

Page 32: ...in pre production devices Factory programmable in production devices 6 Digital I2C Bus Always enabled Option to disable Factory programmable only 7 Digital Configuration CRC Can be disabled by the use...

Page 33: ...cations in the Low Noise LDO Features table 5 Updated the output discharge configurable range in the Low Noise LDO Configurable Settings table 5 Changed the EVM Configurations 6 Updated the TPS650330...

Page 34: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Page 35: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Page 36: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Page 37: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Page 38: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Page 39: ...are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and...

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