Output Voltage Regulation
2-6
2.4
Output Voltage Regulation
The output voltage load regulation of the TPS54973EVM−017 is shown in
Figure 2−4, while the output voltage line regulation is shown in Figure 2−5.
Measurements are shown for an ambient temperature of 25
°
C
Figure 2−4. Load Regulation
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
IO − Output Current − A
− Output V
oltage Change − %
V
O
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
0
1
2
3
4
5
6
7
8
9
10
VI = 3.3 V
Figure 2−5. Line Regulation
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
VI − Input Voltage − V
− Output V
oltage Change − %
V
O
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
3
3.2
3.4
3.6
3.8
4
IO = 0 A
IO = 9 A
IO = 4.5 A
Summary of Contents for TPS54973EVM-017
Page 1: ...E September 2003 PMP Systems Power User s Guide SLVU091...
Page 6: ...iv...
Page 29: ...Layout 3 3 Board Layout Figure 3 2 Internal Layer 2 Figure 3 3 Internal Layer 3...
Page 30: ...Layout 3 4 Figure 3 4 Bottom Side Layout Figure 3 5 Top Side Assembly...
Page 31: ...Layout 3 5 Board Layout Figure 3 6 Bottom Layer Assembly...