Copyright © 2017, Texas Instruments Incorporated
EVM Schematic, Layout Guidelines and PCB Assembly, Layer Plots
16
SLUUBQ7 – August 2017
Copyright © 2017, Texas Instruments Incorporated
TPS2388EVM-612: PoE PSE Evaluation Module for TPS2388
5.2
Layout Guidelines
5.2.1
Supply Voltage Decoupling
Provide power supply pin bypass to the TPS2388 device as follows:
•
0.1 µF, 100 V, X7R ceramic at pin 28 (VPWR)
•
0.1 µF, 50 V, X7R ceramic at pin 1 (VDD)
5.2.2
Port Current Kelvin Sensing
KSENSA is shared between SEN1 and SEN2, while KSENSB is shared between SEN3 and SEN4. In
order to optimize the accuracy of the measurement, the PCB layout must be done carefully to minimize
the impact of PCB trace resistance. Refer to
as an example.
5.2.3
Ground Plane Spacing and Isolation (GND, GND1, and EARTH nets)
Appropriate spacing should be provided between the GND, GND1, and EARTH nets as shown in
5.3
PCB Drawings
through
show the PCB layouts and assemblies for this EVM.
Figure 11. TPS2388EVM-612 (Motherboard) Top Side Assembly
