Texas Instruments TPL5010, User Manual, Page: 16 / 22

GND
GND
J1.2
J1.3
J1.4
J1.5
J1.6
J1.7
J1.8
J1.9
J1.10
+5V
J3.3
J3.4
J3.5
J3.6
J3.7
J3.8
J3.9
J3.10
J4.2
J4.3
J4.4
J4.5
J4.6
J4.7
J4.8
J4.9
J4.10
J2.3
J2.4
J2.6
J2.7
J2.8
J2.10
J4.1
GND
GND
GND
VDD
I_SEL shorted, TPL5010 supplied by battery/external
supply
I_SEL open, current consumption measured with
DMM placed between pin 1 and 2 of I_SEL.
BT
SH-J2
VDD
GND
GND
GND
1
2
3
R_SEL
R_SEL 3-2 shorted, R_EXT set by trimmer.
R_SEL 1-2 shorted R_EXT set by fix resistors
1 2
I_SEL
SH-J1
0.1µF
C1
GND
3
1
2
4
5 6
S1
PVB4 OA 300 NS LFS
Green
1
2
D1
3
1
2
-50V
Q1
AUX_VDD
AUX_VDD
GND
Super Red
1
2
D2
301
R4
1
2
3
Q2
301
R5
AUX_VDD
GND
0
REXT_2
1
2 3
4
S2
4-1437565-1
AUX_VDD
Female headers to connect the TPL5010EVM to the launchpad MSP430F5529
1
2
RST
1
2
VCC
Female headers to disconnect the PowerSupply and
RST signal of the micro present on the launchpad
4
1
2
3
IO
WAKE
DONE
GND
200k ohm
TRIM
FID2
FID1
FID3
SV601108
B PCB Number:
PCB Rev:
LOGO
PCB
Texas Instruments
V_BATT
AUX_VDD
AUX_VDD
VDD
1
GND
2
DELAY/M_RST
3
DONE
4
WAKE
5
RST
6
U1
TPL5010DDC
499
REXT_1
100k
RP
AUX_VDD
5
4
6
7 3
1
2
S_ON_OFF
EG1257
SH-J5
SH-J4
SH-J3
AUX_VDD
Assembly Note
ZZ2
Place shunt SH-J2 on R_SEL
Assembly Note
ZZ3
Place shunt SH-J3 on J1, 3-5
Assembly Note
ZZ1
Place shunt SH-J1 on I_SEL
Assembly Note
ZZ4
Place shunt SH-J4 on J1, 4-6
Assembly Note
ZZ5
Place shunt SH-J5 on J2, 1-2
1
3
5
6
4
2
7
9
10
8
12 11
14
13
16 15
18 17
20 19
J1/J3
66953-010LF
1
3
5
6
4
2
7
9
10
8
12
11
14 13
16 15
18 17
20 19
J4/J2
66953-010LF
RSTn
WAKE
DONE
100k
RD
GND
WAKE
RSTn
DONE
AUX_VDD
GND
0.1µF
C2
RSTn
1
2
3
4
5
6
J1
AUX_VDD
GND
1 2
J2
Schematic
www.ti.com
5 Schematic
Figure 15 illustrates the TPL5010EVM schematic.
Figure 15. TPL5010EVM Schematic
16 TPL5010 Evaluation Module SNAU173 – January 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated