3.1.5 EALLOW Protection
3.2
Steps to Configure eCAN
Steps to Configure eCAN
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To protect against inadvertent modification, some critical registers/bits of the eCAN module are EALLOW
protected. These registers/bits can be changed only if the EALLOW protection has been disabled.
Following are the registers/ bits that are EALLOW protected in the eCAN module:
•
CANMC[15..9] & MCR[7..6]
•
CANBTC
•
CANGIM
•
MIM[31..0]
•
TSC[31..0]
•
IOCONT1[3]
•
IOCONT2[3]
Note:
This sequence must be done with EALLOW enabled.
The following steps must be performed to configure the eCAN for operation:
Step 1.
Enable clock to the CAN module.
Step 2.
Set the CANTX and the CANRX pins to CAN functions:
a. Write CANTIOC.3:0 = 0x08
b. Write CANRIOC.3:0 = 0x08
Step 3.
After a reset, bit CCR (CANMC.12) and bit CCE (CANES.4) are set to 1. This allows the user
to configure the bit-timing configuration register (CANBTC).
If the CCE bit is set (CANES.4 = 1), proceed to next step; otherwise, set the CCR bit
(CANMC.12 = 1) and wait until CCE bit is set (CANES.4 = 1).
Step 4.
Program the CANBTC register with the appropriate timing values. Make sure that the values
TSEG1 and TSEG2 are not 0. If they are 0, the module does not leave the initialization mode.
Step 5.
For the SCC, program the acceptance masks now. For example:
Write LAM(3) = 0x3C0000
Step 6.
Program the master control register (CANMC) as follows:
a. Clear CCR (CANMC.12) = 0
b. Clear PDR (CANMC.11) = 0
c. Clear DBO (CANMC.10) = 0
d. Clear WUBA (CANMC.9)= 0
e. Clear CDR (CANMC.8) = 0
f.
Clear ABO (CANMC.7) = 0
g. Clear STM (CANMC.6) = 0
h. Clear SRES (CANMC.5) = 0
i.
Clear MBNR (CANMC.4-0) = 0
Step 7.
Initialize all bits of MSGCTRLn registers to zero.
Step 8.
Verify the CCE bit is cleared (CANES.4 = 0), indicating that the CAN module has been
configured.
This completes the setup for the basic functionality.
eCAN Configuration
72
SPRU074F – May 2002 – Revised January 2009