SPRZ200E
TMS320VC5509A Silicon Errata
24
Bus Busy Bit Does Not Reflect the State of the I
2
C Bus When the I
2
C is in Reset
Advisory I2C_6
Revision(s) Affected:
1.0 and 1.1
Details:
The Bus Busy bit (BB) indicates the status of the I
2
C bus. The Bus Busy bit is set to ‘0’ when
the bus is free and set to ‘1’ when the bus is busy. The I
2
C peripheral cannot detect the state
of the I
2
C bus when it is in reset (IRS bit is set to ‘0’); therefore, the Bus Busy bit will keep the
state it was at when the peripheral was placed in reset. The Bus Busy bit will stay in that state
until the I
2
C peripheral is taken out of reset (IRS bit set to ‘1’) and a START condition is
detected on the I
2
C bus. When the device is powered up, the Bus Busy bit will stay stuck at
the default value of ‘0’ until the IRS bit is set to ‘1’ and the I
2
C peripheral detects a START
condition.
Systems using a multi-master configuration can be affected by this issue.
Assembler Notification:
None
Workaround:
Wait a certain period after taking the I
2
C peripheral out of reset (setting the IRS bit to ‘1’)
before starting the first data transfer. The period should be set equal to or larger than the total
time it takes for the longest data transfer in the application. By waiting this amount of time, it
can be ensured that any previous transfers finished. After this point, BB will correctly reflect
the state of the I
2
C bus.
DMA Receive Synchronization Pulse Gets Generated Falsely
Advisory I2C_8
Revision(s) Affected:
1.0 and 1.1
Details:
When receiving an I
2
C data stream in master mode (i.e., a read is performed), and the DMA is
started, a DMA synchronization event is triggered upon enabling the DMA channel if a byte is
present in the DRR (even if it has already been read). This leads to the first byte read being a
duplicate of the previous byte that was already read from the DRR.
Assembler Notification:
None
Workaround:
Set DMA transfers from DRR to read one more byte than necessary and discard the first byte.
