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Texas Instruments TMS320VC5509A, Manual

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Texas Instruments TMS320VC5509A Manual Download Page 18

SPRZ200E

TMS320VC5509A Silicon Errata

17

SETUP = 2 Configuration is not Valid for Asynchronous Memory

Advisory EMIF_14

Revision(s) Affected:

1.0 and 1.1

Details:

When using the EMIF in asynchronous memory mode, a read or write SETUP time setting of
two clocks actually behaves like timing of one clock of setup time.

Assembler Notification:

None

Workaround:

If a read setup time of two clocks is required for asynchronous memory, a value of three clock
cycles must be used.

Summary of Contents for TMS320VC5509A

Page 1: ...The content and copyrights of the attached material are the property of its owner Distributed by www Jameco com 1 800 831 4242 Jameco Part Number 1519867 Errata ...

Page 2: ...TMS320VC5509A Digital Signal Processor Silicon Errata SPRZ200E June 2003 Revised April 2008 Copyright 2005 Texas Instruments Incorporated ...

Page 3: ...ted Interrupts Durring CLKGEN Domain Idle PAGE S NO ADDITIONS CHANGES DELETIONS 28 Updated Section 3 12 Power Management Advisories Advisory PM_1 Changed the Title from Repeated Interrupts During CPU Idle to Repeated Interrupts During CLKGEN Domain Idle Details Changed instances of CPU in idle state from CPU to CLKGEN Workaround Changed instances of CPU in idle state from CPU to CLKGEN ...

Page 4: ...ops Block Transfer 13 DMA_2 DMA Does Not Support Burst Transfers From EMIF to EMIF 13 3 5 External Memory Interface EMIF Advisories 14 EMIF_8 ARDY Pin Requires Strong Pullup Resistor 14 EMIF_9 External Memory Write After Read Reversal 14 EMIF_10 Block Write Immediately Following a Block Read May Cause Data Corruption 15 EMIF_11 EMIF Asynchronous Access Hold 0 is Not Valid for Strobe 3 15 EMIF_12 8...

Page 5: ... Than Recommended Speed 48 MHz 22 3 9 Inter Integrated Circuit I2C Advisories 23 I2C_3 ARDY Interrupt is not Generated Properly in Non Repeat Mode if STOP Bit is Set 23 I2C_5 Repeated Start Mode Does Not Work 23 I2C_6 Bus Busy Bit Does Not Reflect the State of the I2C Bus When the I2C is in Reset 24 I2C_8 DMA Receive Synchronization Pulse Gets Generated Falsely 24 3 10 Multichannel Buffered Serial...

Page 6: ...TMDX through fully qualified production devices tools TMS TMDS Device development evolutionary flow TMX Experimental device that is not necessarily representative of the final device s electrical specifications TMP Final silicon die that conforms to the device s electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Support tool d...

Page 7: ... TMP at the beginning of the device name TMX320 4 XXXXXXX VC5509APGE Lot Trace Code Revision 1 0 TMS320 4A XXXXXXX VC5509APGE Lot Trace Code Revision 1 1 Figure 1 Example Markings for VC5509A PGE Package Revisions 1 0 and 1 1 NOTE Early revisions may have a letter D in front of VC5509A in the GHH package TMX320 4 XXXXXXX VC5509AGHH Lot Trace Code Revision 1 0 TMS320 4A XXXXXXX VC5509AGHH Lot Trace...

Page 8: ...509A device the Seconds Alarm Register RTCSECA cannot be used to generate an alarm every second but the update ended interrupt can The Real Time Clock RTC executes an update cycle once per second to update the current time in the time calendar registers Seconds Register RTCSEC Minutes Register RTCMIN Hours Register RTCHOUR Day of the Week and Day Alarm Register RTCDAYW Day of the Month Date Regist...

Page 9: ...rruption 1 0 and 1 1 15 EMIF_11 EMIF Asynchronous Access Hold 0 is Not Valid for Strobe 3 1 0 and 1 1 15 EMIF_12 8 Bit Asynchronous Writes on 5509A EMIF Not Supported 1 0 and 1 1 16 EMIF_13 After Changing CE Control Registers and Disabling SDRAM Clock in Divide by 8 and Divide by 16 Modes Asynchronous Access Followed by SDRAM Access Will Not Supply a Ready Signal to CPU 1 0 and 1 1 16 EMIF_14 SETU...

Page 10: ...tate of the I2C Bus When the I2C is in Reset 1 0 and 1 1 24 I2C_8 DMA Receive Synchronization Pulse Gets Generated Falsely 1 0 and 1 1 24 Multichannel Buffered Serial Port McBSP Advisories MCBSP_1 McBSP May Not Generate a Receive Event to DMA When Data Gets Copied From RSR to DRR 1 0 and 1 1 25 Emulation Advisories EMU_1 Emulation Prone to Failure Under Certain Situations 1 0 and 1 1 26 Power Mana...

Page 11: ...I Instruction may Affect the XF State Advisory DL_7 Revision s Affected 1 0 and 1 1 Details The XF pin state is saved on the stack as a part of the ST1 context saving during interrupts servicing If the XF pin state is changed inside the ISR upon execution of the RETI the XF bit will be restored to the value prior to entering the ISR If XF state is not changed inside the ISR then there is no issue ...

Page 12: ...will be serviced as soon as the DMA TX channel is enabled This transmitted data will remain valid on the bus as long as the McBSP is disabled However once the McBSP is enabled it sends out another DMA TX request and the DMA transmits the second word This results in the loss of the first word of data on consecutive DMA transmissions Assembler Notification None Workaround Only the systems where McBS...

Page 13: ...r Notification None Workaround Ignore the DescriptorType returned by the DSP String Descriptor is not necessary for successfully bootloading the device through the USB USB Bootloader Returns Incorrect PID During Enumeration Phase Advisory BL_4 Revision s Affected 1 0 and 1 1 Details The correct PID is 0x9003 however the bootloader reports 0x9001 to the host Assembler Notification None Workaround P...

Page 14: ...and the channel becomes disabled Assembler Notification None Workaround Ensure that the duration between the sync events is long enough to allow the block transfer to complete The DMA end of block interrupt can be used as an indicator DMA Does Not Support Burst Transfers From EMIF to EMIF Advisory DMA_2 Revision s Affected 1 0 and 1 1 Details The DMA controller does not support burst mode transfer...

Page 15: ...nd Pull up ARDY with a 2 2 kΩ resistor External Memory Write After Read Reversal Advisory EMIF_9 Revision s Affected 1 0 and 1 1 Details If an external memory write is followed immediately by an external memory read the external memory read will occur first followed by the write See the example below Example MOV 1770h 100001h External Memory Write MOV 100000h AR1 External Memory Read Assembler Not...

Page 16: ...o addr2 Read addr2 Assembler Notification None Workaround Insert two NOPs between write and read Since reads occur before writes in the pipeline the read must be delayed after the write so that the read does not occur before the write EMIF Asynchronous Access Hold 0 is Not Valid for Strobe 3 Advisory EMIF_11 Revision s Affected 1 0 and 1 1 Details For asynchronous EMIF accesses a hold time of 0 is...

Page 17: ...MEM is set to divide by 8 and divide by 16 of the CPU clock and if the user disables the SDRAM clock before accessing asynchronous memory the EMIF will fail to supply the ready signal to the CPU under the following two conditions Case 1 SDRAM access Switch off the SDRAM clock Change CE Space Control Register to Asynchronous Mode Perform an asynchronous access to the same CE space Case 2 SDRAM acce...

Page 18: ...fected 1 0 and 1 1 Details When using the EMIF in asynchronous memory mode a read or write SETUP time setting of two clocks actually behaves like timing of one clock of setup time Assembler Notification None Workaround If a read setup time of two clocks is required for asynchronous memory a value of three clock cycles must be used ...

Page 19: ...emented read is performed after this the EHPI address used will be twice the incremented version Assembler Notification N A Workaround Muxed Mode Following a sequence of EHPI write s perform a HPIA update before initiating an EHPI read access Non Muxed Mode Following a sequence of EHPI write s add a dummy HPID read before initiating the actual EHPI read access HPIC HPIA Access Following an Autoinc...

Page 20: ... This is only a problem when a single system has devices that have ready signals that are used in conjunction with the DSP s HRDY signal This could include a single system with multiple DSPs using their HRDY signals in conjunction to signal a master device of their ready status Workaround Logically AND all ready signals with the DSP s HRDY signal to generate a valid ready status ...

Page 21: ...seems to the user that the interrupt was triggered one second earlier For example an alarm set to every minute alarm generates an interrupt at xx xx 59 instead of xx xx 00 Assembler Notification None Workaround Take into account the one second difference when using the alarm interrupt Any Year Ending in 00 Will Appear as a Leap Year Advisory RTC_4 Revision s Affected 1 0 and 1 1 Details Since the ...

Page 22: ...transition from Midnight and Noon should be the following 11 59am 12 00pm 12 59pm 1 00pm 11 59pm 12 00am 12 59am 1 00am However if the RTC is used in the 12h time format the transitions around Noon and Midnight are as below 11 59am 12 00am 12 59am 1 00pm 11 59pm 12 00pm 12 59pm 1 00am Assembler Notification None Workaround The problem can be worked around using the 24h mode ...

Page 23: ...s Placed in IDLE Advisory USB_5 Revision s Affected 1 0 and 1 1 Details USB input cells are always powered unless the oscillator is disabled Assembler Notification None Workaround None CPU Read Write to USB Module may Return Incorrect Result if the USB Clock is Running Slower Than Recommended Speed 48 MHz Advisory USB_6 Revision s Affected 1 0 and 1 1 Details If the CPU speed is x12 or higher than...

Page 24: ...C sends the STOP condition and clears the ARDY bit Assembler Notification None Workaround If the ARDY interrupt is desired after sending data start the data transfer without setting the STP bit If the STOP bit is not set beforehand the master will not send the STOP condition and asserts the ARDY interrupt after sending the data Set the STP bit when the last ARDY interrupt arrives all data sent out...

Page 25: ...iguration can be affected by this issue Assembler Notification None Workaround Wait a certain period after taking the I2C peripheral out of reset setting the IRS bit to 1 before starting the first data transfer The period should be set equal to or larger than the total time it takes for the longest data transfer in the application By waiting this amount of time it can be ensured that any previous ...

Page 26: ...ied to the DRR When this condition occurs the McBSP overwrites the DRR before the DMA had an opportunity to read its value This problem arises when the DRR read occurs at the exact moment the REVT needs to be generated The DRR servicing gets delayed if there are other heavy DMA channels or CPU activities on the peripheral bus Assembler Notification None Workaround Optimize the peripheral bus acces...

Page 27: ...oblem might look similar to the one shown in Figure 3 A TCK edge that does not cause the problem will look similar to the one shown in Figure 4 The key difference between the two figures is that Figure 4 has a clean and sharp transition whereas Figure 3 has a knee in the transition zone Problematic TCK signals may not have a knee that is as pronounced as the one in Figure 3 Due to the TCK signal a...

Page 28: ...around As the problem may be caused by one or more of the above factors one or more of the steps outlined below may be necessary to fix it Avoid using a socket Ensure the board design achieves rise times and fall times of less than 3 ns with clean monotonic edges for the TCK signal For designs where TCK is supplied by the emulation pod use a C55x Emulation Adapter Board part number DSP8102U To ord...

Page 29: ...le state the associated interrupt flag is set again This causes the CPU to exit the idle state and if the associated interrupt enable bit is set the interrupt service routine will also be executed In case of CLKGEN in idle and the external interrupt is driven low to wake up the CPU repeated interrupt will be generated until the external interrupt signal driven high after the CPU wakes up When the ...

Page 30: ... lines Two U R or M results are computed during each cycle by the data path according to the instruction being executed by the accelerator for the M results set the results are denoted as M0 and M1 When Rounding Mode Rnd in the above picture is set to 1 the faulty data path section is implemented M0 A B C D 2 4 which is the correct result but when Rounding Mode is set to 0 the data path section im...

Page 31: ...5 block 1 0 DR0 2 DR0 2 AC3 DR0 rounding_control AC3 2 rounding_control DR1 DR1 1 DR1 block_size 2 rnd_temp AC3 rnd_temp 2 rounding_control DR1 DR1 1 DR1 block_size 2 1 BRC1 DR1 BRC1 block_size 2 1 XAR3 XDP AR3 AR3 rnd_temp AR3 rnd_temp localrepeat repeat blk_size times AC0 AR4 16 AR5 16 AC0 b i j b i 1 j AC0 AC0 AR3 16 AC0 AC0 rnd localrepeat AC1 AR4 16 AR5 16 AC0 b i j 1 b i 1 j 1 AC0 AC0 AC1 AC...

Page 32: ... DSP CPU Reference Guide literature number SPRU371 TMS320C55x DSP Mnemonic Instruction Set Reference Guide literature number SPRU374 TMS320C55x DSP Algebraic Instruction Set Reference Guide literature number SPRU375 TMS320C55x DSP Peripherals Overview Reference Guide literature number SPRU317 TMS320VC5509A Fixed Point Digital Signal Processor data manual literature number SPRS205 TMS320C55x DSP CP...

Page 33: ...usiness practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all neces...

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