Usage Notes and Known Design Exceptions to Functional Specifications
3
SPRZ412K – December 2013 – Revised February 2020
Copyright © 2013–2020, Texas Instruments Incorporated
TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0
4
Usage Notes and Known Design Exceptions to Functional Specifications
4.1
Usage Notes
Usage notes highlight and describe particular situations where the device's behavior may not match
presumed or documented behavior. This may include behaviors that affect device performance or
functional correctness. These usage notes will be incorporated into future documentation updates for the
device (such as the device-specific data sheet), and the behaviors they describe will not be altered in
future silicon revisions.
shows which silicon revision(s) are affected by each usage note.
Table 2. List of Usage Notes
TITLE
SILICON REVISION(S) AFFECTED
0
A
B
C
PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU
Interrupt Mask Clear
Yes
Yes
Yes
Yes
Caution While Using Nested Interrupts
Yes
Yes
Yes
Yes
SYS/BIOS: Version Implemented in Device ROM is not Maintained
Yes
Yes
Yes
Yes
SDFM: Use Caution While Using SDFM Under Noisy Conditions
Yes
Yes
Yes
Yes
4.1.1
PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt
Mask Clear
Revision(s) Affected:
0, A, B, C
Certain code sequences used for nested interrupts allow the CPU and PIE to enter an inconsistent state
that can trigger an unwanted interrupt. The conditions required to enter this state are:
1. A PIEACK clear is followed immediately by a global interrupt enable (EINT or asm(" CLRC INTM")).
2. A nested interrupt clears one or more PIEIER bits for its group.
Whether the unwanted interrupt is triggered depends on the configuration and timing of the other
interrupts in the system. This is expected to be a rare or nonexistent event in most applications. If it
happens, the unwanted interrupt will be the first one in the nested interrupt's PIE group, and will be
triggered after the nested interrupt reenables CPU interrupts (EINT or asm(" CLRC INTM")).
Workaround:
Add a NOP between the PIEACK write and the CPU interrupt enable. Example code is
shown below.
//Bad interrupt nesting code
PieCtrlRegs.PIEACK.all = 0xFFFF;
//Enable nesting in the PIE
EINT;
//Enable nesting in the CPU
//Good interrupt nesting code
PieCtrlRegs.PIEACK.all = 0xFFFF;
//Enable nesting in the PIE
asm(" NOP");
//Wait for PIEACK to exit the pipeline
EINT;
//Enable nesting in the CPU
4.1.2
Caution While Using Nested Interrupts
Revision(s) Affected:
0, A, B, C
If the user is enabling interrupts using the EINT instruction inside an interrupt service routine (ISR) in order
to use the nesting feature, then the user must disable the interrupts before exiting the ISR. Failing to do so
may cause undefined behavior of CPU execution.