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TMS320DM646x DMSoC

Ethernet Media Access Controller (EMAC)/

Management Data Input/Output (MDIO)

Module

User's Guide

Literature Number: SPRUEQ6

December 2007

Summary of Contents for TMS320DM646x

Page 1: ...TMS320DM646x DMSoC Ethernet Media Access Controller EMAC Management Data Input Output MDIO Module User s Guide Literature Number SPRUEQ6 December 2007 ...

Page 2: ...2 SPRUEQ6 December 2007 Submit Documentation Feedback ...

Page 3: ...ol Module Emulation Control Register CMEMCONTROL 62 3 4 EMAC Control Module Interrupt Control Register CMINTCTRL 63 3 5 EMAC Control Module Receive Threshold Interrupt Enable Register CMRXTHRESHINTEN 64 3 6 EMAC Control Module Receive Interrupt Enable Register CMRXINTEN 64 3 7 EMAC Control Module Transmit Interrupt Enable Register CMTXINTEN 65 3 8 EMAC Control Module Miscellaneous Interrupt Enable...

Page 4: ...NTMASKCLEAR 94 5 11 MAC Input Vector Register MACINVECTOR 95 5 12 MAC End Of Interrupt Vector Register MACEOIVECTOR 95 5 13 Receive Interrupt Status Unmasked Register RXINTSTATRAW 96 5 14 Receive Interrupt Status Masked Register RXINTSTATMASKED 97 5 15 Receive Interrupt Mask Set Register RXINTMASKSET 98 5 16 Receive Interrupt Mask Clear Register RXINTMASKCLEAR 99 5 17 MAC Interrupt Status Unmasked...

Page 5: ...E 119 5 43 MAC Address Low Bytes Register MACADDRLO 120 5 44 MAC Address High Bytes Register MACADDRHI 121 5 45 MAC Index Register MACINDEX 121 5 46 Transmit Channel 0 7 DMA Head Descriptor Pointer Register TXnHDP 122 5 47 Receive Channel 0 7 DMA Head Descriptor Pointer Register RXnHDP 122 5 48 Transmit Channel 0 7 Completion Pointer Register TXnCP 123 5 49 Receive Channel 0 7 Completion Pointer R...

Page 6: ...cond Register CMRXINTMAX 70 26 EMAC Control Module Transmit Interrupts per Millisecond Register CMTXINTMAX 70 27 MDIO Version Register VERSION 71 28 MDIO Control Register CONTROL 72 29 PHY Acknowledge Status Register ALIVE 73 30 PHY Link Status Register LINK 73 31 MDIO Link Status Change Interrupt Unmasked Register LINKINTRAW 74 32 MDIO Link Status Change Interrupt Masked Register LINKINTMASKED 75...

Page 7: ... RXnFREEBUFFER 109 69 MAC Control Register MACCONTROL 110 70 MAC Status Register MACSTATUS 112 71 Emulation Control Register EMCONTROL 114 72 FIFO Control Register FIFOCONTROL 114 73 MAC Configuration Register MACCONFIG 115 74 Soft Reset Register SOFTRESET 115 75 MAC Source Address Low Bytes Register MACSRCADDRLO 116 76 MAC Source Address High Bytes Register MACSRCADDRHI 116 77 MAC Hash Address Re...

Page 8: ...TXINTMAX Field Descriptions 70 24 Management Data Input Output MDIO Registers 71 25 MDIO Version Register VERSION Field Descriptions 71 26 MDIO Control Register CONTROL Field Descriptions 72 27 PHY Acknowledge Status Register ALIVE Field Descriptions 73 28 PHY Link Status Register LINK Field Descriptions 73 29 MDIO Link Status Change Interrupt Unmasked Register LINKINTRAW Field Descriptions 74 30 ...

Page 9: ...ter RXnFLOWTHRESH Field Descriptions 108 67 Receive Channel n Free Buffer Count Register RXnFREEBUFFER Field Descriptions 109 68 MAC Control Register MACCONTROL Field Descriptions 110 69 MAC Status Register MACSTATUS Field Descriptions 112 70 Emulation Control Register EMCONTROL Field Descriptions 114 71 FIFO Control Register FIFOCONTROL Field Descriptions 114 72 MAC Configuration Register MACCONF...

Page 10: ...ed peripherals and other technical collateral is available in the C6000 DSP product folder at www ti com c6000 SPRUEP8 TMS320DM646x DMSoC DSP Subsystem Reference Guide Describes the digital signal processor DSP subsystem in the TMS320DM646x Digital Media System on Chip DMSoC SPRUEP9 TMS320DM646x DMSoC ARM Subsystem Reference Guide Describes the ARM subsystem in the TMS320DM646x Digital Media Syste...

Page 11: ...the TMS320C64x digital signal processor DSP megamodule Included is a discussion on the internal direct memory access IDMA controller the interrupt controller the power down controller memory protection bandwidth management and the memory and cache SPRUEQ6 December 2007 Read This First 11 Submit Documentation Feedback ...

Page 12: ...I interface to the physical layer device PHY Full duplex gigabit operation half duplex not supported EMAC acts as DMA master to either internal or external device memory space Hardware error handling including CRC Eight receive channels with VLAN tag discrimination for receive quality of service QOS support Eight transmit channels with round robin or fixed priority for transmit quality of service ...

Page 13: ...ect operation The module is designed to allow almost transparent operation of the MDIO interface with very little maintenance from the core processor The EMAC module provides an efficient interface between the processor and the networked community The EMAC on this device supports 10Base T 10 Mbits second and 100BaseTX 100 Mbits second in either half duplex or full duplex mode and 1000BaseT 1000 Mb...

Page 14: ...ive clocks are fixed by the IEEE 802 3 specification as 2 5 MHZ at 10 Mbps 25 MHZ at 100 Mbps 125 MHZ at 1000 Mbps All EMAC logic is clocked synchronously with the PLL peripheral clock The MDIO clock can be controlled through the application software by programming the divide down factor in the MDIO control register CONTROL In the 10 100 Mbps mode the transmit and receive clock sources are provide...

Page 15: ...fs in terms of cache performance and throughput when descriptors are placed in the system memory versus when they are placed in the EMAC s internal memory Cache performance is improved when the buffer descriptors are placed in internal memory However the EMAC throughput is better when the descriptors are placed in the local EMAC RAM The DM646x DMSoC supports both MII interface for 10 100 Mbps oper...

Page 16: ...tinuous clock that provides the timing reference for receive operations The MRXD MRXDV and MRXER signals are tied to this clock The clock is generated by the PHY and is 2 5 MHZ at 10 Mbps operation and 25 MHZ at 100 Mbps operation MRXD 3 0 I Receive data MRXD The receive data pins are a collection of 4 data signals comprising 4 bits of data MRDX0 is the least significant bit LSB The signals are sy...

Page 17: ... GMTCLK O GMII source synchronous transmit clock GMTCLK This clock is used in 1000 Mbps mode only providing a continuous 125 MHZ frequency for transmit operations The MTXD and MTXEN signals are tied to this clock when in Gigabit mode The clock is generated by the EMAC and is 125 MHZ RFTCLK I Reference transmit clock RFTCLK The reference transmit clock is a continuous clock that provides the timing...

Page 18: ...V I Receive data valid MRXDV The receive data valid signal indicates that the MRXD pins are generating nibble data for use by the EMAC It is driven synchronously to MRCLK MRXER I Receive error MRXER The receive error signal is asserted for one or more MRCLK periods to indicate that an error was detected in the received frame This is meaningful only during data reception when MRXDV is active MDCLK ...

Page 19: ...ended It may be an individual or multicast including broadcast address When the destination EMAC port receives an Ethernet frame with a destination address that does not match any of its MAC physical addresses and no promiscuous multicast or broadcast channel is enabled it discards the frame Source 6 Source address This field contains the MAC address of the Ethernet port that transmits the frame t...

Page 20: ... frame without detecting signal energy from other Ethernet devices the port is done with the frame 4 If the port detects signal energy from other ports while transmitting it stops transmitting its frame and instead transmits a 48 bit jam signal 5 After transmitting the jam signal the port enters an exponential backoff phase Specifically when transmitting a given frame after experiencing a number o...

Page 21: ... an empty buffer ready to receive packet data during receive operations 2 Buffer Offset The buffer offset is the offset from the start of the packet buffer to the first byte of valid data This field only has meaning when the buffer descriptor points to a buffer that actually contains data Buffer Length The buffer length is the actual number of valid packet data bytes stored in the buffer If the bu...

Page 22: ...ptor or first descriptor of a list to the corresponding HDP register Note that the last descriptor in the list must have its next pointer cleared to 0 This is the only way the EMAC has of detecting the end of the list So in the case where only a single descriptor is added its next descriptor pointer must be initialized to 0 The HDP must never be written to a second time while a previous list is ac...

Page 23: ...he system configuration determines whether or not an active interrupt actually interrupts the CPU In general the individual interrupts for different events from the EMAC and MDIO must be enabled in the EMAC control module and it also must be mapped in the ARM interrupt controller and enabled as a CPU interrupt If the system is configured properly the interrupt for a specific receive or transmit ch...

Page 24: ...Example 1 Transmit Buffer Descriptor in C Structure Format EMAC Descriptor The following is the format of a single buffer descriptor on the EMAC typedef struct _EMAC_Desc struct _EMAC_Desc pNext Pointer to next descriptor in chain Uint8 pBuffer Pointer to data buffer Uint32 BufOffLen Buffer Offset MSW and Length LSW Uint32 PktFlgLen Packet Flags MSW and Length LSW EMAC_Desc Packet Flags define EMA...

Page 25: ...er are to be ignored by the EMAC and that valid buffer data starts on byte 16 of the buffer The software application must set this value prior to adding the descriptor to the active transmit list This field is not altered by the EMAC Note that this value is only checked on the first descriptor of a given packet where the start of packet SOP flag is set It can not be used to specify the offset of s...

Page 26: ...he transmit list next descriptor pointer is NULL The software application can use this bit to detect when the EMAC transmitter for the corresponding channel has halted This is useful when the application appends additional packet descriptors to a transmit queue list that is already owned by the EMAC Note that this flag is valid on EOP descriptors only This flag is used when a transmit queue is bei...

Page 27: ...tion may alter this pointer to point to a newly appended descriptor The EMAC will use the new pointer value and proceed to the next descriptor unless the pNext value has already been read In this latter case the receiver will halt the receive channel in question and the software application may restart it at that time The software can detect this case by checking for an end of queue EOQ condition ...

Page 28: ...DSC_FLAG_ALIGNERROR 0x00040000u define EMAC_DSC_FLAG_CRCERROR 0x00020000u define EMAC_DSC_FLAG_NOMATCH 0x00010000u This 16 bit field must be initialized to zero by the software application before adding the descriptor to a receive queue Whether or not this field is updated depends on the setting of the RXBUFFEROFFSET register When the offset register is set to a non zero value the received packet ...

Page 29: ...t SOP and EOP flags are set Otherwise the descriptor pointing to the last packet buffer for the packet has the EOP flag set This flag is initially cleared by the software application before adding the descriptor to the receive queue This bit is set by the EMAC on EOP descriptors When set this flag indicates that the descriptor is currently owned by the EMAC This flag is set by the software applica...

Page 30: ...ived packet is an oversized frame and was not discarded because the RXCEFEN bit was set in the RXMBPENABLE This flag is set by the EMAC in the SOP buffer descriptor if the received packet is only a packet fragment and was not discarded because the RXCEFEN bit was set in the RXMBPENABLE This flag is set by the EMAC in the SOP buffer descriptor if the received packet is undersized and was not discar...

Page 31: ...upt control and pacing logic control Figure 9 EMAC Control Module Block Diagram The EMAC control module includes 8K bytes of internal memory The internal memory block is essential for allowing the EMAC to operate more independently of the CPU It also prevents memory underflow conditions when the EMAC issues read or write requests to descriptor memory Memory accesses to read or write the actual Eth...

Page 32: ...he interrupting channel s 3 Write the appropriate CPGMAC transmit channel n completion pointer register s TXnCP with the address of the last buffer descriptor of the last packet processed by the application software 4 Write the MAC end of interrupt vector register MACEOIVECTOR in the EMAC module with a value of 2h to signal the end of the transmit interrupt processing The EMAC control module recei...

Page 33: ...us interrupt status register CMMISCINTSTAT Upon reception of a miscellaneous pulse interrupt the ISR performs the following 1 Read CMMISCINTSTAT to determine which of the four condition s caused the interrupt 2 Process those interrupts accordingly 3 Write the MAC end of interrupt vector register MACEOIVECTOR in the EMAC module with a value of 3h to signal the end of the miscellaneous interrupt pro...

Page 34: ...PHY device has been detected the MDIO module reads the MDIO PHY link status register LINK to monitor the PHY link state Link change events are stored in the MDIO module which can interrupt the CPU This storing of the events allows the CPU to poll the link status of the PHY device without continuously performing MDIO module accesses However when the CPU must access the MDIO module for configuration...

Page 35: ...INKINTENB bit in USERPHYSELn Reads and writes to registers in this PHY device are performed using the MDIO user access register USERACCESSn The MDIO module powers up in an idle state until specifically enabled by setting the ENABLE bit in the MDIO control register CONTROL At this time the MDIO clock divider and preamble mode selection are also configured The MDIO preamble is enabled by default but...

Page 36: ...ERACCESSn is cleared 2 Write to the GO WRITE REGADR PHYADR and DATA bits in USERACCESSn corresponding to the PHY and PHY register you want to write 3 The write operation to the PHY is scheduled and completed by the MDIO module Completion of the write operation can be determined by polling the GO bit in USERACCESSn for a 0 4 Completion of the operation sets the corresponding USERINTRAW bit 0 or 1 i...

Page 37: ...er reads does not follow the procedure outlined in Section 2 7 2 3 Since the MDIO PHY alive status register ALIVE is used to initially select a PHY it is assumed that the PHY is acknowledging read operations It is possible that a PHY could become inactive at a future point in time An example of this would be a PHY that can have its MDIO addresses changed while the system is running It is not very ...

Page 38: ... The receive path includes receive DMA engine receive FIFO and MAC receiver The transmit path includes transmit DMA engine transmit FIFO and MAC transmitter Statistics logic State RAM Interrupt controller Control registers and logic Clock and reset logic Figure 11 EMAC Module Block Diagram The receive DMA engine is the interface between the receive FIFO and the system core It interfaces to the CPU...

Page 39: ...FO and the CPU It interfaces to the CPU through the bus arbiter in the EMAC control module The transmit FIFO consists of 24 cells of 64 bytes each and associated control logic This enables a packet of 1518 bytes standard Ethernet packet size to be sent without the possibility of underrun The FIFO buffers data in preparation for transmission The MAC transmitter formats frame data from the transmit ...

Page 40: ...or packet fragment in the system s internal or external memory For receive operations each 16 byte descriptor represents a free packet buffer or buffer fragment On both transmit and receive an Ethernet packet is allowed to span one or more memory fragments represented by one 16 byte descriptor per fragment In typical operation there is only one descriptor per receive buffer but transmit packets ma...

Page 41: ...revents further frame reception based on the number of free buffers available Receive buffer flow control issues flow control collisions in half duplex mode and IEEE 802 3X pause frames for full duplex mode Receive buffer flow control is triggered when the number of free buffers in any enabled receive channel free buffer count register RXnFREEBUFFER is less than or equal to the receive channel flo...

Page 42: ...following the completion of the frame currently being transmitted The pause frame contains the maximum possible value for the pause time FFFFh The EMAC counts the receive pause frame time decrements FF00h to 0 and retransmits an outgoing pause frame if the count reaches 0 When the flow control request is removed the EMAC transmits a pause frame with a zero pause time to cancel the pause request No...

Page 43: ...to enhance performance is enabled when the TXPACE bit is set Adaptive performance pacing introduces delays into the normal transmission of frames delaying transmission attempts between stations reducing the probability of collisions occurring during heavy traffic as indicated by frame deferrals and collisions thereby increasing the chance of successful transmission When a frame is deferred suffers...

Page 44: ...lse The EMAC transmit pause timer immediately is set to the new pause frame pause time value Any remaining pause time from the previous pause frame is discarded If the TXFLOWEN bit in MACCONTROL is cleared then the pause timer immediately expires The EMAC does not start the transmission of a new data frame any sooner than 512 bit times after a pause frame with a nonzero pause time has finished bei...

Page 45: ...eive frames with a matching unicast or multicast destination address The RXBROADEN bit in the receive multicast broadcast promiscuous channel enable register RXMBPENABLE determines if broadcast frames are enabled or filtered If broadcast frames are enabled then they are copied to only a single channel selected by the RXBROADCH field in RXMBPENABLE The RXMULTEN bit in RXMBPENABLE determines if hash...

Page 46: ...ype The two octets immediately following the protocol type contain the 16 bit TCI field Bits 15 13 of the TCI field contain the received frames priority 0 to 7 The received frame is a low priority frame if the priority value is 0 to 3 the received frame is a high priority frame if the priority value is 4 to 7 All frames that have a length type field value not equal to 81 00h are low priority frame...

Page 47: ...ytes and the value in the receive maximum length register RXMAXLEN bytes in length inclusive and contain no code align or CRC errors Received frames are long frames if their frame count exceeds the value in RXMAXLEN The RXMAXLEN reset default value is 5EEh 1518 in decimal Long received frames are either oversized or jabber frames Long frames with no errors are oversized frames long frames with CRC...

Page 48: ...tment Summary Address Match RXCAFEN RXCEFEN RXCMFEN RXCSFEN Receive Frame Treatment 0 0 X X X No frames transferred 0 1 0 0 0 Proper frames transferred to promiscuous channel 0 1 0 0 1 Proper undersized data frames transferred to promiscuous channel 0 1 0 1 0 Proper data and control frames transferred to promiscuous channel 0 1 0 1 1 Proper undersized data and control frames transferred to promisc...

Page 49: ...l operation a frame that overruns after starting the frame reception is filtered and the appropriate statistic s are incremented however the RXCEFEN bit in the receive multicast broadcast promiscuous channel enable register RXMBPENABLE affects overrun frame treatment Table 7 shows how the overrun condition is handled for the middle of frame overrun Table 7 Middle of Frame Overrun Treatment Address...

Page 50: ...host of the channel teardown The corresponding transmit channel n completion pointer register TXnCP contains the value FFFF FFFCh The host should acknowledge a teardown interrupt with an FFFF FFFCh acknowledge value Channel teardown may be commanded on any channel at any time The host is informed of the teardown completion by the set teardown complete TDOWNCMPLT buffer descriptor bit The EMAC does...

Page 51: ...formation on the master peripherals priorities see the device specific data manual Peripheral clock and reset control is done through the Power and Sleep Controller PSC module included with the device For more on how the EMAC MDIO and EMAC control module are disabled or placed in reset at runtime from the registers located in the PSC module see Section 2 17 Note For proper operation both the EMAC ...

Page 52: ...errupts using an interrupt retrigger count based on the peripheral clock PLL1 6 There is also an 8K block of RAM local to the EMAC that is used to hold packet buffer descriptors Note that although the EMAC control module and the EMAC module have slightly different functions in practice the type of maintenance performed on the EMAC control module is more commonly conducted from the EMAC module soft...

Page 53: ..._COUNT C_RX_IMAX 0x4 4 RX intt ms EmacControlRegs INTR_COUNT C_TX_IMAX 0x4 4 TX intt ms EmacControlRegs INT_CONTROL 0x30000 bit16 bit17 for enabling TX and Rx intt pacing EmacControlRegs INT_CONTROL 0x258 600 clocks of 150MHz in 4us time endif Initialize MDIO and EMAC Module Discussed later in this document Enable all the EMAC MDIO interrupts in the control module EmacControlRegs CONTROL C_RX_EN 0...

Page 54: ...code for this may appear as in Example 5 Example 5 MDIO Module Initialization Code define PCLK 99 Enable MDIO and setup divider MDIO_REGS CONTROL CSL_FMKT MDIO_CONTROL_ENABLE YES CSL_FMK MDIO_CONTROL_CLKDIV PCLK If the MDIO module is to operate on an interrupt basis the interrupts can be enabled at this time using the MDIO user command complete interrupt mask set register USERINTMASKSET for regist...

Page 55: ...e channel n flow control threshold register RXnFLOWTHRESH and receive filter low priority frame threshold register RXFILTERLOWTHRESH if buffer flow control is to be enabled 8 Most device drivers open with no multicast addresses so clear the MAC address hash registers MACHASH1 and MACHASH2 to 0 9 Write the receive buffer offset register RXBUFFEROFFSET value typically zero 10 Initially clear all uni...

Page 56: ... that remain asserted until the triggering condition is cleared by the host Each of the eight threshold interrupts may be individually enabled by setting the corresponding bit in the receive interrupt mask set register RXINTMASKSET to 1 Each of the eight channel interrupts may be individually disabled by clearing the corresponding bit in the receive interrupt mask clear register RXINTMASKCLEAR to ...

Page 57: ... the register value The host written value is compared to the register content which was written by the EMAC and if the two values are equal then the interrupt is removed otherwise the interrupt remains asserted The host may process multiple packets prior to acknowledging an interrupt or the host may acknowledge interrupts for every packet The receive DMA engine has eight channels which each chann...

Page 58: ...PEND is issued if enabled under error conditions dealing with the handling of buffer descriptors detected during transmit or receive DMA transactions The failure of the software application to supply properly formatted buffer descriptors results in this error The error bit can only be cleared by resetting the EMAC module in hardware The host error interrupt is enabled by setting the HOSTMASK bit i...

Page 59: ...corresponding USERINTMASKED bit is also set in the MDIO user command complete interrupt register USERINTMASKED The interrupt is cleared by writing back the same bit to USERINTMASKED write to clear All the interrupts signaled from the EMAC and MDIO modules are level driven so if they remain active their level remains constant the CPU core requires edge triggered interrupts In order to properly conv...

Page 60: ...nformation on the use of the processor Power and Sleep Controller PSC see the TMS320DM646x DMSoC ARM Subsystem Reference Guide SPRUEP9 Note For correct operation the EMAC and EMAC control module must both be suspended Thus the EMCONTROL and CMEMCONTROL registers must be configured alike EMAC emulation control is implemented for compatibility with other peripherals The SOFT and FREE bits in the emu...

Page 61: ...scellaneous Interrupt Status Register Section 3 12 70h CMRXINTMAX Receive Interrupts Per Millisecond Register Section 3 13 74h CMTXINTMAX Transmit Interrupts Per Millisecond Register Section 3 14 The identification and version register CMIDVER is shown in Figure 13 and described in Table 10 Figure 13 EMAC Control Module Identification and Version Register CMIDVER 31 16 EWIDENT R 2Dh 15 11 10 8 7 0...

Page 62: ...Register CMEMCONTROL 31 16 Reserved R 0 15 2 1 0 Reserved SOFT FREE R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 12 EMAC Control Module Emulation Control Register CMEMCONTROL Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 SOFT Emulation soft bit This bit is used in conjunction with FREE bit to determine the emulation suspend mode This bit h...

Page 63: ...d only n value after reset Table 13 EMAC Control Module Interrupt Control Register CMINTCTRL Field Descriptions Bit Field Value Description 31 Reserved 0 Reserved 30 18 Reserved 0 Reserved 17 16 INTPACEEN 0 3h Interrupt pacing enable Bit 16 1 enables Rx_Pulse Pacing 0 disables pacing Bit 17 1 enables Tx_Pulse Pacing 0 disables pacing 15 12 Reserved 0 Reserved 11 0 INTPRESCALE 0 7FFh Interrupt coun...

Page 64: ...onding channel n receive threshold interrupt Bit n 0 channel n receive threshold interrupt RXTHRESHPENDn is disabled Bit n 1 channel n receive threshold interrupt RXTHRESHPENDn is enabled The receive interrupt enable register CMRXINTEN is shown in Figure 18 and described in Table 15 Figure 18 EMAC Control Module Receive Interrupt Enable Register CMRXINTEN 31 16 Reserved R 0 15 8 7 0 Reserved RXPUL...

Page 65: ...R W Read Write R Read only n value after reset Table 16 EMAC Control Module Transmit Interrupt Enable Register CMTXINTEN Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 TXPULSEEN n Transmit interrupt TXPENDn enable Each bit controls the corresponding channel n transmit interrupt Bit n 0 channel n transmit interrupt TXPENDn is disabled Bit n 1 channel n transmit interrup...

Page 66: ...ed 0 Reserved 3 STATPENDINTEN EMAC module statistics interrupt STATPEND enable 0 EMAC module statistics interrupt STATPEND is disabled 1 EMAC module statistics interrupt STATPEND is enabled 2 HOSTPENDINTEN EMAC module host error interrupt HOSTPEND enable 0 EMAC module host error interrupt HOSTPEND is disabled 1 EMAC module host error interrupt HOSTPEND is enabled 1 LINKINTEN MDIO module link chang...

Page 67: ...atus of the corresponding channel n receive threshold interrupt Bit n 0 channel n receive threshold interrupt is not pending Bit n 1 channel n receive threshold interrupt is pending The receive interrupt status register CMRXINTSTAT is shown in Figure 22and described in Table 19 Figure 22 EMAC Control Module Receive Interrupt Status Register CMRXINTSTAT 31 16 Reserved R 0 15 8 7 0 Reserved RXPULSEI...

Page 68: ... 0 R 0 LEGEND R Read only n value after reset Table 20 EMAC Control Module Transmit Interrupt Status Register CMTXINTSTAT Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 TXPULSEINTTSTAT n Transmit interrupt status Each bit shows the status of the corresponding channel n transmit interrupt Bit n 0 channel n transmit interrupt is not pending Bit n 1 channel n transmit int...

Page 69: ...STATPENDINTSTAT EMAC module statistics interrupt STATPEND status 0 EMAC module statistics interrupt STATPEND is not pending 1 EMAC module statistics interrupt STATPEND is pending 2 HOSTPENDINTSTAT EMAC module host error interrupt HOSTPEND status 0 EMAC module host error interrupt HOSTPEND is not pending 1 EMAC module host error interrupt HOSTPEND is pending 1 LINKINTSTAT MDIO module link change in...

Page 70: ...umber of interrupts per millisecond generated on RX_PULSE if pacing is enabled for this interrupt Valid values are 2 to 63 0 1h Reserved The transmit interrupts per millisecond register CMTXINTMAX is shown in Figure 26and described in Table 23 Figure 26 EMAC Control Module Transmit Interrupts per Millisecond Register CMTXINTMAX 31 16 Reserved R 0 15 6 5 0 Reserved TXIMAX R 0 R W 0 LEGEND R W Read ...

Page 71: ...and Complete Interrupt Mask Set Register Section 4 9 2Ch USERINTMASKCLEAR MDIO User Command Complete Interrupt Mask Clear Register Section 4 10 80h USERACCESS0 MDIO User Access Register 0 Section 4 11 84h USERPHYSEL0 MDIO User PHY Select Register 0 Section 4 12 88h USERACCESS1 MDIO User Access Register 1 Section 4 13 8Ch USERPHYSEL1 MDIO User PHY Select Register 1 Section 4 14 The MDIO version reg...

Page 72: ...annel that is available in the module It is currently set to 1 This implies that MDIOUserAccess1 is the highest available user access channel 23 21 Reserved 0 Reserved 20 PREAMBLE Preamble disable 0 Standard MDIO preamble is used 1 Disables this device from sending MDIO frame preambles 19 FAULT Fault indicator This bit is set to 1 if the MDIO pins fail to read back what the device is driving onto ...

Page 73: ... will clear it writing a 0 has no effect 0 The PHY fails to acknowledge the access 1 The most recent access to the PHY with an address corresponding to the register bit number was acknowledged by the PHY The PHY link status register LINK is shown in Figure 30 and described in Table 28 Figure 30 PHY Link Status Register LINK 31 16 LINK R 0 15 0 LINK R 0 LEGEND R Read only n value after reset Table ...

Page 74: ...scriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 0 LINKINTRAW 0 3h MDIO Link change event raw value When asserted a bit indicates that there was an MDIO link change event that is change in the LINK register corresponding to the PHY address in the USERPHYSEL register LINKINTRAW 0 and LINKINTRAW 1 correspond to USERPHYSEL0 and USERPHYSEL1 respectively Writing a 1 will clear the even...

Page 75: ... 0 Reserved 1 0 LINKINTMASKED 0 3h MDIO Link change interrupt masked value When asserted a bit indicates that there was an MDIO link change event that is change in the LINK register corresponding to the PHY address in the USERPHYSEL register and the corresponding LINKINTENB bit was set LINKINTMASKED 0 and LINKINTMASKED 1 correspond to USERPHYSEL0 and USERPHYSEL1 respectively Writing a 1 will clear...

Page 76: ...ter USERINTRAW Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 0 USERINTRAW 0 3h MDIO User command complete event bits When asserted a bit indicates that the previously scheduled PHY read or write command using that particular USERACCESS register has completed USERINTRAW 0 and USERINTRAW 1 correspond to USERACCESS0 and USERACCESS1 respectively Writing a 1 will clear the e...

Page 77: ...2 Reserved 0 Reserved 1 0 USERINTMASKED 0 3h Masked value of MDIO User command complete interrupt When asserted a bit indicates that the previously scheduled PHY read or write command using that particular USERACCESS register has completed and the corresponding USERINTMASKSET bit is set to 1 USERINTMASKED 0 and USERINTMASKED 1 correspond to USERACCESS0 and USERACCESS1 respectively Writing a 1 will...

Page 78: ...ion 31 2 Reserved 0 Reserved 1 0 USERINTMASKSET 0 3h MDIO user interrupt mask set for USERINTMASKED 1 0 respectively Setting a bit to 1 will enable MDIO user command complete interrupts for that particular USERACCESS register MDIO user interrupt for a particular USERACCESS register is disabled if the corresponding bit is 0 USERINTMASKSET 0 and USERINTMASKSET 1 correspond to USERACCESS0 and USERACC...

Page 79: ...R Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 0 USERINTMASKCLEAR 0 3h MDIO user command complete interrupt mask clear for USERINTMASKED 1 0 respectively Setting a bit to 1 will disable further user command complete interrupts for that particular USERACCESS register USERINTMASKCLEAR 0 and USERINTMASKCLEAR 1 correspond to USERACCESS0 and USERACCESS1 respectively Writing...

Page 80: ...he MDIO state machine is enabled This bit will self clear when the requested access has been completed Any writes to the USERACCESS0 register are blocked when the GO bit is 1 30 WRITE Write enable bit Setting this bit to 1 causes the MDIO transaction to be a register write otherwise it is a register read 0 The user command is a read operation 1 The user command is a write operation 29 ACK 0 1 Ackn...

Page 81: ...t Default value is 0 which implies that the link status is determined by the MDIO state machine This is the only option supported on this device 0 The link status is determined by the MDIO state machine 1 Not supported 6 LINKINTENB Link change interrupt enable Set to 1 to enable link change status interrupts for PHY address specified in PHYADRMON Link change interrupts are disabled if this bit is ...

Page 82: ... MDIO state machine is enabled This bit will self clear when the requested access has been completed Any writes to the USERACCESS0 register are blocked when the GO bit is 1 30 WRITE Write enable bit Setting this bit to 1 causes the MDIO transaction to be a register write otherwise it is a register read 0 The user command is a read operation 1 The user command is a write operation 29 ACK 0 1 Acknow...

Page 83: ...hich implies that the link status is determined by the MDIO state machine This is the only option supported on this device 0 The link status is determined by the MDIO state machine 1 Not supported 6 LINKINTENB Link change interrupt enable Set to 1 to enable link change status interrupts for the PHY address specified in PHYADRMON Link change interrupts are disabled if this bit is set to 0 0 Link ch...

Page 84: ...eive Multicast Broadcast Promiscuous Channel Enable Register Section 5 21 104h RXUNICASTSET Receive Unicast Enable Set Register Section 5 22 108h RXUNICASTCLEAR Receive Unicast Clear Register Section 5 23 10Ch RXMAXLEN Receive Maximum Length Register Section 5 24 110h RXBUFFEROFFSET Receive Buffer Offset Register Section 5 25 114h RXFILTERLOWTHRESH Receive Filter Low Priority Frame Threshold Regis...

Page 85: ...ptor Pointer Register Section 5 46 61Ch TX7HDP Transmit Channel 7 DMA Head Descriptor Pointer Register Section 5 46 620h RX0HDP Receive Channel 0 DMA Head Descriptor Pointer Register Section 5 47 624h RX1HDP Receive Channel 1 DMA Head Descriptor Pointer Register Section 5 47 628h RX2HDP Receive Channel 2 DMA Head Descriptor Pointer Register Section 5 47 62Ch RX3HDP Receive Channel 3 DMA Head Descr...

Page 86: ...smit Frames Register Section 5 50 17 244h TXDEFERRED Deferred Transmit Frames Register Section 5 50 18 248h TXCOLLISION Transmit Collision Frames Register Section 5 50 19 24Ch TXSINGLECOLL Transmit Single Collision Frames Register Section 5 50 20 250h TXMULTICOLL Transmit Multiple Collision Frames Register Section 5 50 21 254h TXEXCESSIVECOLL Transmit Excessive Collision Frames Register Section 5 ...

Page 87: ...version value Revisions are indicated by a revision code taking the format TXMAJORVER TXMINORVER Ah Current transmit major version value 7 0 TXMINORVER Transmit minor version value Revisions are indicated by a revision code taking the format TXMAJORVER TXMINORVER 7h Current transmit minor version value The transmit control register TXCONTROL is shown in Figure 42 and described in Table 41 Figure 4...

Page 88: ...Bit Field Value Description 31 3 Reserved 0 Reserved 2 0 TXTDNCH 0 7h Transmit teardown channel The transmit channel teardown is commanded by writing the encoded value of the transmit channel to be torn down The teardown register is read as 0 0 Teardown transmit channel 0 1h Teardown transmit channel 1 2h Teardown transmit channel 2 3h Teardown transmit channel 3 4h Teardown transmit channel 4 5h ...

Page 89: ...version value Revisions are indicated by a revision code taking the format RXMAJORVER RXMINORVER Ah Current receive major version value 7 0 RXMINORVER Receive minor version value Revisions are indicated by a revision code taking the format RXMAJORVER RXMINORVER 7h Current receive minor version value The receive control register RXCONTROL is shown in Figure 45 and described in Table 44 Figure 45 Re...

Page 90: ...ns Bit Field Value Description 31 3 Reserved 0 Reserved 2 0 RXTDNCH 0 7h Receive teardown channel The receive channel teardown is commanded by writing the encoded value of the receive channel to be torn down The teardown register is read as 0 0 Teardown receive channel 0 1h Teardown receive channel 1 2h Teardown receive channel 2 3h Teardown receive channel 3 4h Teardown receive channel 4 5h Teard...

Page 91: ...able 46 Transmit Interrupt Status Unmasked Register TXINTSTATRAW Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 TX7PEND 0 1 TX7PEND raw interrupt read before mask 6 TX6PEND 0 1 TX6PEND raw interrupt read before mask 5 TX5PEND 0 1 TX5PEND raw interrupt read before mask 4 TX4PEND 0 1 TX4PEND raw interrupt read before mask 3 TX3PEND 0 1 TX3PEND raw interrupt read before mas...

Page 92: ...END R Read only n value after reset Table 47 Transmit Interrupt Status Masked Register TXINTSTATMASKED Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 TX7PEND 0 1 TX7PEND masked interrupt read 6 TX6PEND 0 1 TX6PEND masked interrupt read 5 TX5PEND 0 1 TX5PEND masked interrupt read 4 TX4PEND 0 1 TX4PEND masked interrupt read 3 TX3PEND 0 1 TX3PEND masked interrupt read 2 TX2...

Page 93: ...to enable interrupt a write of 0 has no effect 6 TX6MASK 0 1 Transmit channel 6 interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect 5 TX5MASK 0 1 Transmit channel 5 interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect 4 TX4MASK 0 1 Transmit channel 4 interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect 3 TX3MASK 0 1 Transm...

Page 94: ...to disable interrupt a write of 0 has no effect 6 TX6MASK 0 1 Transmit channel 6 interrupt mask clear bit Write 1 to disable interrupt a write of 0 has no effect 5 TX5MASK 0 1 Transmit channel 5 interrupt mask clear bit Write 1 to disable interrupt a write of 0 has no effect 4 TX4MASK 0 1 Transmit channel 4 interrupt mask clear bit Write 1 to disable interrupt a write of 0 has no effect 3 TX3MASK ...

Page 95: ...PEND 0 FFh Transmit channels 0 7 interrupt pending TXPENDn status bit Bit 16 is transmit channel 0 15 8 RXTHRESHPEND 0 FFh Receive threshold channels 0 7 interrupt pending RXTHRESHPENDn status bit Bit 8 is receive channel 0 7 0 RXPEND 0 FFh Receive channels 0 7 interrupt pending RXPENDn status bit Bit 0 is receive channel 0 The MAC end of interrupt vector register MACEOIVECTOR is shown in Figure 5...

Page 96: ...ble 52 Receive Interrupt Status Unmasked Register RXINTSTATRAW Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 RX7PEND 0 1 RX7PEND raw interrupt read before mask 6 RX6PEND 0 1 RX6PEND raw interrupt read before mask 5 RX5PEND 0 1 RX5PEND raw interrupt read before mask 4 RX4PEND 0 1 RX4PEND raw interrupt read before mask 3 RX3PEND 0 1 RX3PEND raw interrupt read before mask ...

Page 97: ...ND R Read only n value after reset Table 53 Receive Interrupt Status Masked Register RXINTSTATMASKED Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 RX7PEND 0 1 RX7PEND masked interrupt read 6 RX6PEND 0 1 RX6PEND masked interrupt read 5 RX5PEND 0 1 RX5PEND masked interrupt read 4 RX4PEND 0 1 RX4PEND masked interrupt read 3 RX3PEND 0 1 RX3PEND masked interrupt read 2 RX2PE...

Page 98: ... channel 7 mask set bit Write 1 to enable interrupt a write of 0 has no effect 6 RX6MASK 0 1 Receive channel 6 mask set bit Write 1 to enable interrupt a write of 0 has no effect 5 RX5MASK 0 1 Receive channel 5 mask set bit Write 1 to enable interrupt a write of 0 has no effect 4 RX4MASK 0 1 Receive channel 4 mask set bit Write 1 to enable interrupt a write of 0 has no effect 3 RX3MASK 0 1 Receive...

Page 99: ...annel 7 mask clear bit Write 1 to disable interrupt a write of 0 has no effect 6 RX6MASK 0 1 Receive channel 6 mask clear bit Write 1 to disable interrupt a write of 0 has no effect 5 RX5MASK 0 1 Receive channel 5 mask clear bit Write 1 to disable interrupt a write of 0 has no effect 4 RX4MASK 0 1 Receive channel 4 mask clear bit Write 1 to disable interrupt a write of 0 has no effect 3 RX3MASK 0 ...

Page 100: ...nterrupt HOSTPEND raw interrupt read before mask 0 STATPEND 0 1 Statistics pending interrupt STATPEND raw interrupt read before mask The MAC interrupt status masked register MACINTSTATMASKED is shown in Figure 58 and described in Table 57 Figure 58 MAC Interrupt Status Masked Register MACINTSTATMASKED 31 16 Reserved R 0 15 2 1 0 Reserved HOSTPEND STATPEND R 0 R 0 R 0 LEGEND R Read only n value aft...

Page 101: ...ffect 0 STATMASK 0 1 Statistics interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect The MAC interrupt mask clear register MACINTMASKCLEAR is shown in Figure 60 and described in Table 59 Figure 60 MAC Interrupt Mask Clear Register MACINTMASKCLEAR 31 16 Reserved R 0 15 2 1 0 Reserved HOSTMASK STATMASK R 0 R W1C 0 R W1C 0 LEGEND R Read only R W Read Write W1C Write 1 to clea...

Page 102: ...is enabled 28 RXNOCHAIN Receive no buffer chaining bit 0 Received frames can span multiple buffers 1 The Receive DMA controller transfers each frame into a single buffer regardless of the frame or buffer size All remaining frame data after the first buffer is discarded The buffer descriptor buffer length field will contain the entire frame byte count up to 65535 bytes 27 25 Reserved 0 Reserved 24 ...

Page 103: ...l 3 to receive promiscuous frames 4h Select channel 4 to receive promiscuous frames 5h Select channel 5 to receive promiscuous frames 6h Select channel 6 to receive promiscuous frames 7h Select channel 7 to receive promiscuous frames 15 14 Reserved 0 Reserved 13 RXBROADEN Receive broadcast enable Enable received broadcast frames to be copied to the channel selected by RXBROADCH bits 0 Broadcast fr...

Page 104: ...e multicast frames 1h Select channel 1 to receive multicast frames 2h Select channel 2 to receive multicast frames 3h Select channel 3 to receive multicast frames 4h Select channel 4 to receive multicast frames 5h Select channel 5 to receive multicast frames 6h Select channel 6 to receive multicast frames 7h Select channel 7 to receive multicast frames 104 Ethernet Media Access Controller EMAC Man...

Page 105: ...ffect May be read 6 RXCH6EN 0 1 Receive channel 6 unicast enable set bit Write 1 to set the enable a write of 0 has no effect May be read 5 RXCH5EN 0 1 Receive channel 5 unicast enable set bit Write 1 to set the enable a write of 0 has no effect May be read 4 RXCH4EN 0 1 Receive channel 4 unicast enable set bit Write 1 to set the enable a write of 0 has no effect May be read 3 RXCH3EN 0 1 Receive ...

Page 106: ...he enable a write of 0 has no effect 6 RXCH6EN 0 1 Receive channel 6 unicast enable clear bit Write 1 to clear the enable a write of 0 has no effect 5 RXCH5EN 0 1 Receive channel 5 unicast enable clear bit Write 1 to clear the enable a write of 0 has no effect 4 RXCH4EN 0 1 Receive channel 4 unicast enable clear bit Write 1 to clear the enable a write of 0 has no effect 3 RXCH3EN 0 1 Receive chann...

Page 107: ...ve buffer offset register RXBUFFEROFFSET is shown in Figure 65 and described in Table 64 Figure 65 Receive Buffer Offset Register RXBUFFEROFFSET 31 16 Reserved R 0 15 0 RXBUFFEROFFSET R W 0 LEGEND R Read only R W Read Write n value after reset Table 64 Receive Buffer Offset Register RXBUFFEROFFSET Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 0 RXBUFFEROFFSET 0 FFFFh ...

Page 108: ... filter low threshold These bits contain the free buffer count threshold value for filtering low priority incoming frames This field should remain 0 if no filtering is desired The receive channel 0 7 flow control threshold register RXnFLOWTHRESH is shown in Figure 67 and described in Table 66 Figure 67 Receive Channel n Flow Control Threshold Register RXnFLOWTHRESH 31 16 Reserved R 0 15 8 7 0 Rese...

Page 109: ...ee buffers available The RXFILTERTHRESH value is compared with this field to determine if low priority frames should be filtered The RXnFLOWTHRESH value is compared with this field to determine if receive flow control should be issued against incoming packets if enabled This is a write to increment field This field rolls over to 0 on overflow If hardware flow control or QOS is used the host must i...

Page 110: ...ord to any receive buffer descriptor 13 RXOWNERSHIP Receive ownership write bit value 0 EMAC writes the Receive ownership bit to 0 at the end of packet processing 1 EMAC writes the Receive ownership bit to 1 at the end of packet processing If you do not use the ownership mechanism you can set this mode to preclude the necessity of software having to set this bit each time the buffer descriptor is ...

Page 111: ...UFFERFLOWEN Receive buffer flow control enable bit 0 Receive flow control is disabled Half duplex mode no flow control generated collisions are sent Full duplex mode no outgoing pause frames are sent 1 Receive flow control is enabled Half duplex mode collisions are initiated when receive buffer flow control is triggered Full duplex mode outgoing pause frames are sent when receive flow control is t...

Page 112: ...cket but the SOP bit is not set in software 2h Ownership bit not set in SOP buffer 3h Zero next buffer descriptor pointer without EOP 4h Zero buffer pointer 5h Zero buffer length 6h Packet length error sum of buffers is less than packet length 19 Reserved 0 Reserved 18 16 TXERRCH 0 7h Transmit host error channel These bits indicate which transmit channel the host error occurred on This field is cl...

Page 113: ...ceive quality of service is enabled and that at least one channel freebuffer count RXnFREEBUFFER is less than or equal to the RXFILTERLOWTHRESH value 0 Receive quality of service is disabled 1 Receive quality of service is enabled 1 RXFLOWACT Receive flow control active bit When asserted at least one channel freebuffer count RXnFREEBUFFER is less than or equal to the channel s corresponding RXnFIL...

Page 114: ...LTHRESH R 0 R W 18h LEGEND R W Read Write R Read only n value after reset Table 71 FIFO Control Register FIFOCONTROL Field Descriptions Bit Field Value Description 31 23 Reserved 0 Reserved 22 16 RXFIFOFLOWTHRESH 0 3Fh Receive FIFO flow control threshold Occupancy of the receive FIFO when receive FIFO flow control is triggered if enabled The default value is 2h which means that receive FIFO flow c...

Page 115: ...guration value The soft reset register SOFTRESET is shown in Figure 74 and described in Table 73 Figure 74 Soft Reset Register SOFTRESET 31 16 Reserved R 0 15 1 0 Reserved SOFTRESET R 0 R W 0 LEGEND R Read only R W Read Write n value after reset Table 73 Soft Reset Register SOFTRESET Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 SOFTRESET Software reset Writing a 1 to t...

Page 116: ...0 7 0 MACSRCADDR1 0 FFh MAC source address bits 15 8 byte 1 The MAC source address high bytes register MACSRCADDRHI is shown in Figure 76 and described in Table 75 Figure 76 MAC Source Address High Bytes Register MACSRCADDRHI 31 24 23 16 MACSRCADDR2 MACSRCADDR3 R W 0 R W 0 15 8 7 0 MACSRCADDR4 MACSRCADDR5 R W 0 R W 0 LEGEND R Read only R W Read Write n value after reset Table 75 MAC Source Address...

Page 117: ...ddress should be accepted or not The MAC hash address register 1 MACHASH1 is shown in Figure 77 and described in Table 76 Figure 77 MAC Hash Address Register 1 MACHASH1 31 16 MACHASH1 R W 0 15 0 MACHASH1 R W 0 LEGEND R Read only R W Read Write n value after reset Table 76 MAC Hash Address Register 1 MACHASH1 Field Descriptions Bit Field Value Description 31 0 MACHASH1 0 FFFF FFFFh Least significan...

Page 118: ...tomatically according to the backoff algorithm and is decremented by one for each slot time after the collision The transmit pacing algorithm test register TPACETEST is shown in Figure 80 and described in Table 79 Figure 80 Transmit Pacing Algorithm Test Register TPACETEST 31 16 Reserved R 0 15 5 4 0 Reserved PACEVAL R 0 R 0 LEGEND R Read only n value after reset Table 79 Transmit Pacing Algorithm...

Page 119: ...mer is decremented at slot time intervals If the receive pause timer decrements to 0 then another outgoing pause frame is sent and the load decrement process is repeated The transmit pause timer register TXPAUSE is shown in Figure 82 and described in Table 81 Figure 82 Transmit Pause Timer Register TXPAUSE 31 16 Reserved R 0 15 0 PAUSETIMER R 0 LEGEND R Read only n value after reset Table 81 Trans...

Page 120: ...0 Address location is not valid and will not be used in determining whether or not an incoming packet matches or is filtered 1 Address location is valid and will be used in determining whether or not an incoming packet matches or is filtered 19 MATCHFILT Match or filter bit 0 The address will be used if the VALID bit is set to determine if the incoming packet address should be filtered 1 The addre...

Page 121: ...he group bit It is forced to 0 and read as 0 Therefore only unicast addresses are represented in the address table The MAC index register MACINDEX is shown in Figure 85 and described in Table 84 Figure 85 MAC Index Register MACINDEX 31 16 Reserved R 0 15 3 2 0 Reserved MACINDEX R 0 R W 0 LEGEND R Read only R W Read Write n value after reset Table 84 MAC Index Register MACINDEX Field Descriptions B...

Page 122: ...riting to these locations when they are nonzero is an error except at reset Host software must initialize these locations to 0 on reset The receive channel 0 7 DMA head descriptor pointer register RXnHDP is shown in Figure 87 and described in Table 86 Figure 87 Receive Channel n DMA Head Descriptor Pointer Register RXnHDP 31 16 RXnHDP R W x 15 0 RXnHDP R W x LEGEND R W Read Write n value after res...

Page 123: ...ssed by the host during interrupt processing The EMAC uses the value written to determine if the interrupt should be deasserted The receive channel 0 7 completion pointer register RXnCP is shown in Figure 89 and described in Table 88 Figure 89 Receive Channel n Completion Pointer Register RXnCP 31 16 RXnCP R W x 15 0 RXnCP R W x LEGEND R W Read Write n value after reset x value is indeterminate af...

Page 124: ...atistics Register 31 16 COUNT R WD 0 15 0 COUNT R WD 0 LEGEND R W Read Write WD Write to decrement n value after reset The total number of good frames received on the EMAC A good frame is defined as having all of the following Any data or MAC control frame that matched a unicast broadcast or multicast address or matched due to promiscuous mode Was of length 64 to RXMAXLEN bytes inclusive Had no CR...

Page 125: ... an even number of nibbles Fails the frame check sequence test See Section 2 5 5 for definitions of alignment code and CRC errors Overruns have no effect on this statistic The total number of frames received on the EMAC that experienced an alignment error or code error Such a frame is defined as having all of the following Was any data or MAC control frame that matched a unicast broadcast or multi...

Page 126: ...bytes long Had no CRC error alignment error or code error See Section 2 5 5 for definitions of alignment code and CRC errors Overruns have no effect on this statistic The total number of frame fragments received on the EMAC A frame fragment is defined as having all of the following Any data frame address matching does not matter Was less than 64 bytes long Had a CRC error alignment error or code e...

Page 127: ...ing free buffer register RXnFREEBUFFER value Was of length 64 to RXMAXLEN RXQOSEN bit is set in RXMBPENABLE Had no CRC error alignment error or code error See Section 2 5 5 for definitions of alignment code and CRC errors Overruns have no effect on this statistic The total number of bytes in all good frames received on the EMAC A good frame is defined as having all of the following Any data or MAC...

Page 128: ...ferment Such a frame is defined as having all of the following Was any data or MAC control frame destined for any unicast broadcast or multicast address Was any size Had no carrier loss and no underrun Experienced no collisions before being successfully transmitted Found the medium busy when transmission was first attempted so had to wait CRC errors have no effect on this statistic The total numbe...

Page 129: ... have no effect on this statistic The total number of frames when transmission was abandoned due to a late collision Such a frame is defined as having all of the following Was any data or MAC control frame destined for any unicast broadcast or multicast address Was any size Had no carrier loss and no underrun Experienced a collision later than 512 bit times into the transmission There may have bee...

Page 130: ...er of 65 byte to 127 byte frames received and transmitted on the EMAC Such a frame is defined as having all of the following Any data or MAC control frame that was destined for any unicast broadcast or multicast address Did not experience late collisions excessive collisions underrun or carrier sense error Was 65 bytes to 127 bytes long CRC errors alignment code errors underruns and overruns do no...

Page 131: ...as all of the following Was any data or MAC control frame destined for any unicast broadcast or multicast address address match does not matter Was of any size including less than 64 byte and greater than RXMAXLEN byte frames Also counted in this statistic is Every byte transmitted before a carrier loss was experienced Every byte transmitted before each collision was experienced multiple retries a...

Page 132: ... successfully started no SOF overrun CRC errors alignment errors and code errors have no effect on this statistic The total number of frames received on the EMAC that had either a DMA start of frame SOF overrun or a DMA middle of frame MOF overrun A receive DMA overrun frame is defined as having all of the following Was any data or MAC control frame that matched a unicast broadcast or multicast ad...

Page 133: ... no contention for a shared medium in this mode Full duplex mode can only be used when all of the following are true The physical medium is capable of supporting simultaneous transmission and reception without interference There are exactly two stations connected with a full duplex point to point link As there is no contention for use of a shared medium the multiple access that is CSMA CD algorith...

Page 134: ... type used by the Ethernet is specified by these fields data rate in Mb s medium type maximum segment length 100m The definitions for the technologies mentioned in this document are in Table A 1 Table A 1 Physical Layer Definitions Term Definition 10Base T IEEE 802 3 Physical Layer specification for a 10 Mb s CSMA CD local area network over two pairs of twisted pair telephone wire 100Base T IEEE 8...

Page 135: ...ice and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyer...

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