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Texas Instruments TMS320C80, User Manual

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Texas Instruments TMS320C80 User Manual Download Page 59

 Running Title—Attribute Reference

A-1

 Chapter Title—Attribute Reference

The ’C80 and ’C82 Memory Maps

The TMS320C8x is a byte-addressable device with a single 4-GB
memory space common to its processors. Each address refers
to a specific byte in the address space. Addresses less than
02000000h are reserved for on-chip memory, and addresses
from 02000000h to FFFFFFFFh are assigned to off-chip
memory. The memory map is shown in Figure A–1 for the ’C80
and in Figure A–2 for the ’C82.

Appendix A

Summary of Contents for TMS320C80

Page 1: ...TMS320C80 to TMS320C82 Software Compatibility User s Guide 1995 Digital Signal Processing Products ...

Page 2: ...SPRU154 Printed in U S A November 1995 M418017 9741 revision ...

Page 3: ...TMS320C80 to TMS320C82 Software Compatibility User s Guide SPRU154 November 1995 Printed on Recycled Paper ...

Page 4: ...NED INTENDED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT APPLICATIONS DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS Inclusion of TI products in such applications is understood to be fully at the risk of the customer Use of TI products in such applications requires the written approval of an appropriate TI officer Questions concerning potential risk applications should be dir...

Page 5: ...nd the C82 Chapter 2 discusses guidelines and techniques for develop ing software that can run on both the C80 and the C82 Chapter 3 discusses guidelines and techniques for prototyp ing C82 software using a C80 If you need background information about the differences be tween the C80 and the C82 read Chapter 1 before going on to Chapter 2 and Chapter 3 If you already understand the differences bet...

Page 6: ...out the features and operation of the debuggers and the parallel debug manager it also includes basic information about C expressions and a description of progress and error messages TMS320C80 Code Generation Tools User s Guide literature number SPRU108 describes the C8x code generation tools This manual provides information about the features and operation of the linker the master processor MP C ...

Page 7: ...provides information about the VC features archi tecture and operation It also includes procedures and ex amples for programming the serial register transfer SRT controller and the frame timer registers If You Need Assistance If you want to Do this Request more information about Texas Instruments Digital Signal Processing DSP products Call the CRC hotline 800 336 5236 Or write to Texas Instruments...

Page 8: ...vi TMS320C80 to TMS320C82 Software Compatibility User s Guide ...

Page 9: ...iques for programming C80 C82 compatible software 2 1 Programming Considerations 2 2 2 2 Obtaining Device Specific Information 2 3 2 2 1 Determining the Device that is Executing your Software MP 2 3 2 2 2 Determining the Device that is Executing your Software PP 2 3 2 2 3 Initializing a PP s Stack Pointer 2 4 2 2 4 Counting the Number of PPs 2 5 2 3 Technique 1 Using Only Common RAM 2 6 2 3 1 Adva...

Page 10: ... PP0 Data RAM 1 and PP1 Data RAM 1 3 3 3 3 Emulating the C82 s Parameter RAMs 3 4 3 3 1 Emulating the PP Parameter RAMs 3 4 3 3 2 Emulating the MP Parameter RAM 3 5 3 4 Prototyping Code Using Linker Command Files 3 6 3 4 1 PP Relative Addressing 3 6 3 4 2 Map Files 3 7 3 4 3 Linking Your C82 Code for Prototyping on a C80 3 7 3 4 4 Linking your Code for a C82 3 11 3 4 5 MP Linker Command Files 3 14...

Page 11: ... 3 C80 and C82 MP Parameter RAM Block Diagram 1 10 1 4 C80 and C82 PP Parameter RAM Block Diagram 1 11 1 5 PP State Information on the Stack at Reset 1 12 2 1 The Type Field in the MP config Register 2 3 2 2 The PP s comm Register 2 3 2 3 Structure of a PP Command Buffer 2 9 A 1 TMS320C80 Memory Map A 2 A 2 TMS320C82 Memory Map A 4 ...

Page 12: ...am 3 8 3 2 C80 PP Linker Command File for example c 3 10 3 3 C80 Map File Lines for Vector A and Vector B 3 11 3 4 C82 PP Linker Command File 3 12 3 5 C82 Map File Lines for Vector A and Vector B 3 13 3 6 C80 MP Linker Command File 3 14 3 7 C82 MP Linker Command File 3 15 3 8 Sample PP C Program With an Assembly Language Function 3 17 3 9 Assembly Language Function to Calculate the Dot Product of ...

Page 13: ...1 8 1 5 3 Caches 1 13 5 Programming for Compatibility 2 1 Provides techniques for programming C80 C82 compatible software 2 1 Programming Considerations 2 2 2 2 Obtaining Device Specific Information 2 3 2 2 1 Determining the Device that is Executing your Software MP 2 3 2 2 2 Determining the Device that is Executing your Software PP 2 3 2 2 3 Initializing a PP s Stack Pointer 2 4 2 2 4 Counting th...

Page 14: ...erview 3 2 3 2 Emulating the C82 s Data RAMs 3 3 3 2 1 Emulating the C82 s Data RAM 0 3 3 3 2 2 Emulating the C82 s PP0 Data RAM 1 and PP1 Data RAM 1 3 3 3 3 Emulating the C82 s Parameter RAMs 3 4 3 3 1 Emulating the PP Parameter RAMs 3 4 3 3 2 Emulating the MP Parameter RAM 3 5 3 3 3 Managing Pointers 3 5 B The C80 and C82 Memory Maps A 1 Provides the memory maps of the C80 and C82 ...

Page 15: ...and C82 MP Parameter RAM Block Diagram 1 10 1 4 C80 and C82 PP Parameter RAM Block Diagram 1 11 1 5 PP State Information on the Stack at Reset 1 12 2 1 The Type Field in the MP config Register 2 3 2 2 The PP s comm Register 2 3 2 3 Structure of a PP Command Buffer 2 9 3 1 Structure of a PP Command Buffer 3 5 A 1 TMS320C80 Memory Map A 2 A 2 TMS320C82 Memory Map A 4 ...

Page 16: ...xiv TMS320C80 to TMS320C82 Software Compatibility User s Guide ...

Page 17: ...ou for the software related discussions in Chapter 2 and Chapter 3 In this chapter you will find information that will help you Understand general differences between the C80 and C82 Understand memory differences between the C80 and C82 Understand the basis for the information in Chapter 2 and Chapter 3 Topics 1 1 Overview of C80 and C82 Features 1 2 1 2 Parallel Processor Differences 1 3 1 3 Tran...

Page 18: ...re if the software is written for compatibility Four main differences relate to compatibility The C80 has four parallel processors the C82 has two The on chip RAM of the C80 is divided into 25 2 KB blocks the on chip RAM of the C82 is divided into 11 4 KB blocks The C80 transfer controller has 7 externally initiated packet transfer XPT requests the C82 transfer controller has 15 The C80 has an on ...

Page 19: ...he C82 has two PPs software written to execute on both the C80 and C82 must not require more than two PPs Software that can use up to four PPs but that requires only two PPs will run on both devices The number of PPs on a chip can be counted through software This allows you to optimize your software s use of available PPs See subsection 2 2 4 Counting the Number of PPs for a descrip tion of how yo...

Page 20: ...r of XPT requests handled by the C80 and C82 is dif ferent However because XPT requests are driven by external devices the seven XPT requests shared by the C80 and C82 generally aren t used to emulate each other in different systems with different peripherals For example the likelihood is small that the peripheral connected to XPT1 on the C80 software de velopment board SDB is the same as the peri...

Page 21: ...deo controller but the C82 does not If the chips are to be used in video applications the portion of your software that sets up the video timing registers needs to be written so that an external video controller can be used with the C82 This is usually just a matter of switching video drivers de pending on the chip being used ...

Page 22: ...ence For your reference the memory maps of the C80 and C82 are described in Appendix A 1 5 1 Data RAMs Data RAMs are standard read write memory with no caching or special features They are the main areas in which the PPs store the data they are processing Any transfer of data to or from data RAMs is done explicitly by the processors either by a direct read from or write to memory or by a request t...

Page 23: ...ÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ Reserved 0000 3800 0000 3FFF PP3 data RAM 1 ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ 4096 bytes 0000 8000 0000 87FF PP0 data RAM 2 PP0 data RAM 1 0000 8800 0000 8FFF ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ Reserved 4096 bytes 0000 9000 0000 97FF PP1 data RAM 2 PP1 data RAM 1 0000 9800 0000 9FFF ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ Reserved 4096 bytes 0000 8000 0000 87FF PP2 data RAM 2 ÉÉ...

Page 24: ...e Figure 1 2 contrasts the memory maps for the on chip parame ter RAM on the C80 and C82 All C80 memory locations occu pied by parameter RAM for PP0 PP1 and the MP are also popu lated on the C82 The memory locations occupied by the C80 s parameter RAMs for PP2 and PP3 are unpopulated on the C82 Each of the C82 s parameter RAMs is 4096 bytes long which is twice the size of each parameter RAM on the...

Page 25: ...ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ 4096 bytes 0100 3000 0100 37FF PP3 parameter RAM ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ Reserved 0100 3800 0100 3FFF ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ Reserved ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ 4096 bytes 0101 0000 0101 07FF MP parameter RAM MP parameter RAM 0101 0800 0101 0FFF ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ Reserved 4096 bytes Figure 1 3 shows the MP parameter RAM in th...

Page 26: ...sses 0101 00E0 0101 00FB 7 XPT linked list addresses 28 bytes 60 bytes 0101 00FC 0101 00FF MP packet transfer linked list address 4 bytes MP packet transfer linked list address 4 bytes 0101 0100 0101 017F Buffer for MP initiated ext to ext transfers 128 bytes Buffer for MP initiated ext to ext transfers 128 bytes 0101 0180 0101 01FF MP interrupt vectors 128 bytes MP interrupt vectors 128 bytes 010...

Page 27: ...arameters 128 bytes Suspended packet parameters 128 bytes 0100 080 0100 0DF ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ Reserved 96 bytes ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ Reserved 96 bytes 0100 0E0 0100 0F7 Restricted for operating system 24 bytes Restricted for operating system 24 bytes 0100 0F8 0100 0FB Cache fault address 4 bytes Cache fault address 4 bytes 0100 0FC 0100 0FF Linked l...

Page 28: ...er IPE onto the stack As shown in Figure 5 this leaves the SP register pointing to address 010017FCh in the C80 and to address 01001FFCh in the C82 For most applications these addresses are likely to be the best choices for the initial SP values because they assign the largest available contiguous block of memory to the combined stack and general purpose areas in the parameter RAM Figure 1 5 PP St...

Page 29: ...he locations of the caches are not important This information is available on the memory maps in Appendix A for your reference Table 1 2 lists the sizes of the caches in the C80 and C82 Bet ter PP performance may occur in the C82 since each C82 PP instruction cache is twice as large as its corresponding C80 PP instruction cache Table 1 2 C80 and C82 Cache Sizes Cache C80 C82 PP instruction cache s...

Page 30: ...1 14 TMS320C80 to TMS320C82 Software Compatibility User s Guide ...

Page 31: ...u will find information that will help you Select the best compatibility technique for your application Write programs that will run on both the C80 and the C82 Write code that can test which device it is running on C80 or C82 Write code that correctly initializes a PP s stack pointer based upon which device it is running on Topics 2 1 Programming Considerations 2 2 2 2 Obtaining Device Specific I...

Page 32: ...low software developed on one device to be used on the other For instance a C80 based board and emulator can serve as a convenient prototyping system for developing code targeted to run on a C82 In fact developing software that will run on both the C80 and C82 without recompiling or relinking is not difficult Writing code that runs on both the C80 and C82 is straightfor ward because of the similar...

Page 33: ...2 in the C80 Type 00102 in the C82 2 2 2 Determining the Device that is Executing your Software PP PP software can determine which device it is running on by read ing the M field bits 15 8 in the comm register which is shown in Figure 2 2 The M field equals 000000002 in the C80 and 000000012 in the C82 Figure 2 2 The PP s comm Register 31 30 29 28 27 16 15 8 7 4 3 2 1 0 H S Q P Reserved M Reserved...

Page 34: ...e SP to the same value it would have immediately following reset This value is 0100 7F0h on the C80 and to 0100 FF0h on the C82 the sign represents the PP number Example 2 1 shows a four instruction code segment written in PP assembly language that sets a PP s stack pointer and comm registers to their initial values The program reads the M bit in the comm register to determine whether it is runnin...

Page 35: ...tion returns an 8 bit mask in which each bit indi cates whether or not PP0 PP7 are present bit 0 corresponds to PP0 bit 1 corresponds to PP1 etc When executed on a C80 de vice the function returns the value 0Fh to indicate that PP0 PP1 PP2 and PP3 are present When executed on a C82 device the function returns the value 03h to indicate that PP0 and PP1 are present Example 2 2 MP C Function for Coun...

Page 36: ...1 This technique offers three main advantages It is simple to implement Performance is nearly identical on the C80 and C82 All of the RAM available to the C80 s MP PP0 and PP1 can be used 2 3 2 Disadvantages of Technique 1 This technique has two main disadvantages All of the RAM available to the C82 cannot be used Contention may result in the C82 since the space occupied by two RAMs data RAM 0 and...

Page 37: ...dule can be performed during any one clock cycle C80 applications may run slightly slower on the C82 because this area of memory can can be accessed only once per clock cycle This can occur when software attempts to access data RAMs 0 and 1 simultaneously The delays caused by this type of contention are usually negligi ble unless a critical inner loop of a PP program written for the C80 contains i...

Page 38: ...ween the memory maps of the C80 and C82 More available memory compared to technique 1 can be used on both devices 2 4 2 Disadvantages of Technique 2 This technique has a two main disadvantages Technique 2 is more complicated than technique 1 One RAM cannot be used since it is needed to store argu ments 2 4 3 Implementing Technique 2 Implement this technique by writing software that performs three ...

Page 39: ... 2 3 Structure of a PP Command Buffer link flag function args mailbox Pointer to next command buffer in linked list Full not empty flag Pointer to command function Pointer to buffer containing argument values Pointer to server PP s mailbox 32 bits msgValue intCode Message to put in mailbox for client Code for message interrupt to client 2 4 4 Considerations When Using Technique 2 In the case of th...

Page 40: ...2 10 TMS320C80 to TMS320C82 Software Compatibility User s Guide ...

Page 41: ...run on the C82 alone In this chapter you will find information that will help you Prototype C82 applications with a C80 Develop C82 code on a C80 development board Topics 3 1 Overview 3 2 3 2 Emulating the C82 s Data RAMs 3 3 3 3 Emulating the C82 s Parameter RAMs 3 4 3 4 Prototyping Code Using Linker Command Files 3 6 Chapter 3 ...

Page 42: ...of the on chip RAM that is common to the C80 and C82 Additionally since the software will be designed to run primarily on the C82 device specific information can be hard coded right into the software This can be accomplished by using linker com mand files that specify the memory configuration of each device For software on the prototype board you would use the linker command file for the C80 In th...

Page 43: ... the C80 s PP0 data RAMs 0 and 1 can directly emulate the C82 s PP0 data RAM 0 This approach also works in emulating the C82 s PP1 data RAM 0 3 2 2 Emulating the C82 s PP0 Data RAM 1 and PP1 Data RAM 1 Emulating the C82 s PP0 data RAM 1 and PP1 data RAM 1 is not quite as straightforward Only the first half of the 4 KB block of memory occupied by each PP s data RAM 1 is populated on the C80 by the ...

Page 44: ... each PP stack so that it starts at the end of the emulated parameter RAM the end of the second block Make sure that each PP stack does not exceed the bound aries of its RAM Keep PP2 and PP3 halted in the C80 3 3 1 Emulating the PP Parameter RAMs The PP parameter RAMs in the C82 are twice the size of the PP parameter RAMs in the C80 The second half of each parameter RAM is not populated in the C80...

Page 45: ... C80 The C80 s PP2 pa rameter RAM can be mapped into this space and accessed via a pointer This approach works only if the application allows two noncontiguous blocks of C80 RAM to be used to emulate a single block of MP parameter RAM This technique uses all 2048 bytes of the C80 s PP2 parameter RAM as general purpose RAM As long as PP2 remains halted the hardware functions that can write to the p...

Page 46: ...or the C80 and then test your code on the C80 3 Link your code with a linker command file for the C82 when you are ready to use that device The software tools for the C80 and C82 come with template link er command files that you will need to modify according to the re quirements of your program For a list of linker directives see Section 13 4 Linker Command Files in the TMS320C80 MVP Code Generati...

Page 47: ...mmand file By examining the map file generated by the linker you can verify that the sections of your program are mapped into the proper locations in memory For more information about map files see subsection 13 3 8 Create a map file m filename option in the TMS320C80 MVP Code Generation Tools User s Guide 3 4 3 Linking Your C82 Code for Prototyping on a C80 Example 3 1 is a sample PP C program th...

Page 48: ...initial value of the accumulator to zero for i 0 i vect_size i dot_prod dot_prod A i B i calculate the dot product return dot_prod 3 4 3 1 Allocating Memory In Sections In the code the vectors are allocated by using the pragma direc tive This directive allocates space in the sections that are de fined in the linker command file A sample pragma directive is as follows pragma DATA_SECTION A a_sect T...

Page 49: ...er command file causes the code to use RAM from other PPs to emulate the RAM in the C82 The method used to create this file is described in Section 3 2 Emulating the C82 s Data RAMs and Section 3 3 Emulating the C82 s Parameter RAMs In the SECTIONS area of the linker command file a_sect is spe cified to be placed in DRAM0 and b_sect is specified to be placed in DRAM1 The directives that accomplish...

Page 50: ...he C source code using the PP compiler 2 Link the output of the compiler with the linker command file shown in Example 3 2 Both of these steps can be accomplished using a single com mand ppcl g example c z o c80ex out m c80ex map c80pp lnk 3 4 3 4 The C80 Map File The map file shows where each variable was linked into memory In this case the linker command file specifically assigns A to DRAM0 and ...

Page 51: ...SYMBOLS address name 00000140 A 00002000 B 3 4 4 Linking your Code for a C82 After prototyping your code on the C80 you can make it execute on the C82 by simply linking the object file using a C82 linker command file In this case you can use the linker command file in this section to link the object file generated by compiling Example 3 1 to create an executable file for the C82 The linker command...

Page 52: ...S DRAM0 a_sect PASS DRAM0 b_sect PASS DRAM1 3 4 4 2 Compiling and Linking example c for the C82 To produce an executable for the C82 link the object file gener ated when you last compiled example c with the linker command file shown in Example 3 4 This step can be accomplished using a single command ppcl z o c82ex out m c82ex map example o c82pp lnk If you do not have an object file to link you ca...

Page 53: ... 01000200 000000e00 RWIX EXTMEM 02000000 000080000 RWIX SECTION ALLOCATION MAP output attributes section page origin length input sections a_sect 0 00000140 00000c00 PASS SECTION 00000140 00000c00 example o a_sect b_sect 0 00008000 00000c00 PASS SECTION 00008000 00000c00 example o b_sect GLOBAL SYMBOLS address name 00000140 A 00008000 B In this example a_sect was placed at address 00000140h in DRA...

Page 54: ...ng C82 code on a C80 Example 3 7 show the command file for linking C82 code to execute on a C82 Example 3 6 C80 MP Linker Command File c80mp lnk MP linker command file for prototyping C82 code on a C80 c x heap 0x2000 stack 0x2000 l mp_rts lib MEMORY EXTMEM o 0x02000000 l 0x80000 MPPRAM0 o 0x01010000 l 0x800 MPPRAM1 o 0x01002000 l 0x800 SECTIONS text EXTMEM ptext EXTMEM bss EXTMEM const EXTMEM swi...

Page 55: ...DRAM1 PP PRAM and MP PRAM is emulated by two RAMs in the C80 In some cases code may run more slowly on the C80 than on the C82 Code that uses the local port to access DRAM1 could cause a 1 cycle stall during each access since DRAM1 is not local to the C80 PPs 3 4 6 1 Contention Differences in the C80 and C82 In the C82 contention exists between accesses to the first half and last half of a RAM In ...

Page 56: ... the C80 can equivalent in terms of timing and functionality In other words the most important consideration in this case is to write the assembly code to avoid different execution times for each processor In the example A is accessed loaded using the local port since it is specifically linked to a portion of memory that is local to the PP that is executing the code B on the other hand is accessed...

Page 57: ...y language function to calculate the dot product The assembly language code has the filename c80ex p include mvp h allocate space for A in a named section asect pragma DATA_SECTION A a_sect allocate space for B in a named section bsect pragma DATA_SECTION B b_sect define a the buffer size for A and B define BUF_SIZE 1536 short A BUF_SIZE short B BUF_SIZE extern long dot_product short short int mai...

Page 58: ...ible to both MP and PP C dot_product _dot_product La_A_ptr a_addr initialize a local address register to vector A Ga_B_ptr b_addr initialize global address register to vector B lrse2 vect_size 1 Use the fast initialization form to set up a single instruction loop The PP executes the instruction at DOT_PROD_LOOP vect_size times prod 0 clear prod A h La_A_ptr load first element of A using the local ...

Page 59: ... with a single 4 GB memory space common to its processors Each address refers to a specific byte in the address space Addresses less than 02000000h are reserved for on chip memory and addresses from 02000000h to FFFFFFFFh are assigned to off chip memory The memory map is shown in Figure A 1 for the C80 and in Figure A 2 for the C82 Appendix A ...

Page 60: ...ed 0000 9000 0000 97FF 2K PP1 Data RAM 2 0000 9800 0000 9FFF 2K ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Reserved 0000 A000 0000 A7FF 2K PP2 Data RAM 2 0000 A800 0000 AFFF 2K ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Reserved 0000 B000 0000 B7FF 2K PP3 Data RAM 2 0000 B800 00FF FFFF 16M ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Reserved 0100 0000 0100 07FF 2...

Page 61: ...ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Reserved 0180 7800 0180 7FFF 2K PP3 Instruction Cache 0180 8000 0180 FFFF 32K ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Reserved 0181 0000 0181 07FF 2K MP Data Cache 0 0181 0800 0181 0FFF 2K MP Data Cache 1 0181 1000 0181 7FFF 28K ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Reserved 0181 8000 0181 87FF 2K MP Instruction Cache 0 0181 8...

Page 62: ...ed 0100 0000 0100 0FFF 4K PP0 Parameter RAM 0100 1000 0100 1FFF 4K PP1 Parameter RAM 0100 2000 0100 FFFF 56K ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Reserved 0101 0000 0101 0FFF 4K MP Parameter RAM 0101 1000 0180 0FFF 8M ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Reserved 0180 1000 0180 1FFF 4K PP0 Instruction Cache 0180 2000 0180 2FFF 4K ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ...

Page 63: ...e 0181 8000 0181 8FFF 4K MP Instruction Cache 0181 9000 0181 FFFF 28K ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Reserved 0182 0000 0182 01FF 512 Memory Mapped TC Registers 0182 0200 01FF FFFF 8M ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Reserved 0200 0000 FFFF FFFF 4G External Memory Block sizes have been rounded to the nearest unit size ...

Page 64: ...A 6 TMS320C80 to TMS320C82 Software Compatibility User s Guide ...

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