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EMAC Control Module Registers

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3.8

EMAC Control Module Interrupt Core Receive Threshold Interrupt Status Registers
(C0RXTHRESHSTAT-C2RXTHRESHSTAT)

The EMAC control module interrupt core 0-2 receive threshold interrupt status register
(CnRXTHRESHSTAT) is shown in

Figure 19

and described in

Table 16

Figure 19. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register

(CnRXTHRESHSTAT)

Reserved

R-0

Reserved

R-0

RXCH7THRESH

RXCH6THRESH

RXCH5THRESH

RXCH4THRESH

RXCH3THRESH

RXCH2THRESH

RXCH1THRESH

RXCH0THRESH

STAT

R-0

LEGEND: R = Read only; -n = value after reset

Table 16. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register

(CnRXTHRESHSTAT)

Bit

Field

Value

Description

31-8

Reserved

RXCH7THRESHSTAT

Interrupt status for RX Channel 7 masked by the CnRXTHRESHEN register

RX Channel 7 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt.

RX Channel 7 satisfies conditions to generate a CnRXTHRESHPULSE interrupt.

RXCH6THRESHSTAT

Interrupt status for RX Channel 6 masked by the CnRXTHRESHEN register

RX Channel 6 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt.

RX Channel 6 satisfies conditions to generate a CnRXTHRESHPULSE interrupt.

RXCH5THRESHSTAT

Interrupt status for RX Channel 5 masked by the CnRXTHRESHEN register

RX Channel 5 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt.

RX Channel 5 satisfies conditions to generate a CnRXTHRESHPULSE interrupt.

RXCH4THRESHSTAT

Interrupt status for RX Channel 4 masked by the CnRXTHRESHEN register

RX Channel 4 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt.

RX Channel 4 satisfies conditions to generate a CnRXTHRESHPULSE interrupt.

RXCH3THRESHSTAT

Interrupt status for RX Channel 3 masked by the CnRXTHRESHEN register

RX Channel 3 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt.

RX Channel 3 satisfies conditions to generate a CnRXTHRESHPULSE interrupt.

RXCH2THRESHSTAT

Interrupt status for RX Channel 2 masked by the CnRXTHRESHEN register

RX Channel 2 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt.

RX Channel 2 satisfies conditions to generate a CnRXTHRESHPULSE interrupt.

RXCH1THRESHSTAT

Interrupt status for RX Channel 1 masked by the CnRXTHRESHEN register

RX Channel 1 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt.

RX Channel 1 satisfies conditions to generate a CnRXTHRESHPULSE interrupt.

RXCH0THRESHSTAT

Interrupt status for RX Channel 0 masked by the CnRXTHRESHEN register

RX Channel 0 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt.

RX Channel 0 satisfies conditions to generate a CnRXTHRESHPULSE interrupt.

EMAC/MDIO Module

SPRUFL5B – April 2011

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Summary of Contents for TMS320C674X

Page 1: ...TMS320C674x OMAP L1x Processor Ethernet Media Access Controller EMAC Management Data Input Output MDIO Module User s Guide Literature Number SPRUFL5B April 2011 ...

Page 2: ...2 SPRUFL5B April 2011 Submit Documentation Feedback 2011 Texas Instruments Incorporated ...

Page 3: ...errupt Control Register INTCONTROL 59 3 4 EMAC Control Module Interrupt Core Receive Threshold Interrupt Enable Registers C0RXTHRESHEN C2RXTHRESHEN 60 3 5 EMAC Control Module Interrupt Core Receive Interrupt Enable Registers C0RXEN C2RXEN 61 3 6 EMAC Control Module Interrupt Core Transmit Interrupt Enable Registers C0TXEN C2TXEN 62 3 7 EMAC Control Module Interrupt Core Miscellaneous Interrupt Ena...

Page 4: ...TATRAW 90 5 8 Transmit Interrupt Status Masked Register TXINTSTATMASKED 91 5 9 Transmit Interrupt Mask Set Register TXINTMASKSET 92 5 10 Transmit Interrupt Mask Clear Register TXINTMASKCLEAR 93 5 11 MAC Input Vector Register MACINVECTOR 94 5 12 MAC End Of Interrupt Vector Register MACEOIVECTOR 95 5 13 Receive Interrupt Status Unmasked Register RXINTSTATRAW 96 5 14 Receive Interrupt Status Masked R...

Page 5: ...Receive Pause Timer Register RXPAUSE 119 5 42 Transmit Pause Timer Register TXPAUSE 119 5 43 MAC Address Low Bytes Register MACADDRLO 120 5 44 MAC Address High Bytes Register MACADDRHI 121 5 45 MAC Index Register MACINDEX 121 5 46 Transmit Channel DMA Head Descriptor Pointer Registers TX0HDP TX7HDP 122 5 47 Receive Channel DMA Head Descriptor Pointer Registers RX0HDP RX7HDP 122 5 48 Transmit Chann...

Page 6: ...terrupt Status Register CnMISCSTAT 67 23 EMAC Control Module Interrupt Core 0 2 Receive Interrupts Per Millisecond Register CnRXIMAX 68 24 EMAC Control Module Interrupt Core 0 2 Transmit Interrupts Per Millisecond Register CnTXIMAX 69 25 MDIO Revision ID Register REVID 70 26 MDIO Control Register CONTROL 71 27 PHY Acknowledge Status Register ALIVE 72 28 PHY Link Status Register LINK 72 29 MDIO Lin...

Page 7: ...low Control Threshold Register RXnFLOWTHRESH 108 66 Receive Channel n Free Buffer Count Register RXnFREEBUFFER 109 67 MAC Control Register MACCONTROL 110 68 MAC Status Register MACSTATUS 112 69 Emulation Control Register EMCONTROL 114 70 FIFO Control Register FIFOCONTROL 114 71 MAC Configuration Register MACCONFIG 115 72 Soft Reset Register SOFTRESET 115 73 MAC Source Address Low Bytes Register MA...

Page 8: ... Register REVID Field Descriptions 70 24 MDIO Control Register CONTROL Field Descriptions 71 25 PHY Acknowledge Status Register ALIVE Field Descriptions 72 26 PHY Link Status Register LINK Field Descriptions 72 27 MDIO Link Status Change Interrupt Unmasked Register LINKINTRAW Field Descriptions 73 28 MDIO Link Status Change Interrupt Masked Register LINKINTMASKED Field Descriptions 74 29 MDIO User...

Page 9: ...riptions 108 65 Receive Channel n Free Buffer Count Register RXnFREEBUFFER Field Descriptions 109 66 MAC Control Register MACCONTROL Field Descriptions 110 67 MAC Status Register MACSTATUS Field Descriptions 112 68 Emulation Control Register EMCONTROL Field Descriptions 114 69 FIFO Control Register FIFOCONTROL Field Descriptions 114 70 MAC Configuration Register MACCONFIG Field Descriptions 115 71...

Page 10: ...s available in the C6000 DSP product folder at www ti com c6000 SPRUGM5 TMS320C6742 DSP System Reference Guide Describes the C6742 DSP subsystem system memory device clocking phase locked loop controller PLLC power and sleep controller PSC power management and system configuration module SPRUGJ0 TMS320C6743 DSP System Reference Guide Describes the System on Chip SoC including the C6743 DSP subsyst...

Page 11: ...eference Guide Describes the CPU architecture pipeline instruction set and interrupts for the TMS320C674x digital signal processors DSPs The C674x DSP is an enhancement of the C64x and C67x DSPs with added functionality and an expanded instruction set SPRUG82 TMS320C674x DSP Cache User s Guide Explains the fundamentals of memory caches and describes how the two level cache based internal memory ar...

Page 12: ...ia Independent Interface MII and or Reduced Media Independent Interface RMII to physical layer device PHY EMAC acts as DMA master to either internal or external device memory space Eight receive channels with VLAN tag discrimination for receive quality of service QOS support Eight transmit channels with round robin or fixed priority for transmit quality of service QOS support Ether Stats and 802 3...

Page 13: ...MDIO interface with very little maintenance from the core processor The EMAC module provides an efficient interface between the processor and the network The EMAC on this device supports 10Base T 10 Mbits sec and 100BaseTX 100 Mbits sec half duplex and full duplex mode and hardware flow control and quality of service QOS support Figure 1 shows the main interface between the EMAC control module and...

Page 14: ... are fixed by the IEEE 802 3 specification as 2 5 MHz at 10 Mbps 25 MHz at 100 Mbps The RMII interface frequency for the transmit and receive clocks are fixed at 50 MHz for both 10 Mbps and 100 Mbps 2 2 Memory Map The EMAC peripheral includes internal memory that is used to hold buffer descriptions of the Ethernet packets to be received and transmitted This internal RAM is 2K 32 bits in size Data ...

Page 15: ...tion the MII_COL pin is used for hardware transmit flow control Asserting the MII_COL pin will stop packet transmissions packets in the process of being transmitted when MII_COL is asserted will complete transmission The MII_COL pin should be held low if hardware transmit flow control is not used MII_CRS I Carrier sense MII_CRS In half duplex operation the MII_CRS pin is asserted by the PHY when t...

Page 16: ...he signals are synchronized by RMII_MHZ_50_CLK and valid only when RMII_TXEN is asserted RMII_TXEN O Transmit enable RMII_TXEN The transmit enable signal indicates that the RMII_TXD pins are generating data for use by the PHY RMII_TXEN is synchronous to RMII_MHZ_50_CLK RMII_MHZ_50_CLK I RMII reference clock RMII_MHZ_50_CLK The reference clock is used to synchronize all RMII signals RMII_MHZ_50_CLK...

Page 17: ...broadcast address When the destination EMAC port receives an Ethernet frame with a destination address that does not match any of its MAC physical addresses and no promiscuous multicast or broadcast channel is enabled it discards the frame Source 6 Source address This field contains the MAC address of the Ethernet port that transmits the frame to the Local Area Network Len 2 Length Type field The ...

Page 18: ...signal energy from other Ethernet devices the port is done with the frame 4 If the port detects signal energy from other ports while transmitting it stops transmitting its frame and instead transmits a 48 bit jam signal 5 After transmitting the jam signal the port enters an exponential backoff phase If a data frame encounters back to back collisions the port chooses a random value that is dependen...

Page 19: ...ions or is an empty buffer ready to receive packet data during receive operations 2 Buffer Offset The buffer offset is the offset from the start of the packet buffer to the first byte of valid data This field only has meaning when the buffer descriptor points to a buffer that actually contains data Buffer Length The buffer length is the actual number of valid packet data bytes stored in the buffer...

Page 20: ...s the pointer to the descriptor or first descriptor of a list to the corresponding HDP register Note that the last descriptor in the list must have its next pointer cleared to 0 This is the only way the EMAC has of detecting the end of the list Therefore in the case where only a single descriptor is added its next descriptor pointer must be initialized to 0 The HDP must never be written to while a...

Page 21: ...opriate interrupt core registers are set in the EMAC control module CnRXEN and CnTXEN on core n 3 The CPU interrupt controller is configured to accept Cn_RX_PULSE and Cn_TX_PULSE interrupts from the EMAC control module Whether or not the interrupt is enabled the current state of the receive or transmit channel interrupt can be examined directly by the software application reading the EMAC receive ...

Page 22: ...ptor on the EMAC typedef struct _EMAC_Desc struct _EMAC_Desc pNext Pointer to next descriptor in chain Uint8 pBuffer Pointer to data buffer Uint32 BufOffLen Buffer Offset MSW and Length LSW Uint32 PktFlgLen Packet Flags MSW and Length LSW EMAC_Desc Packet Flags define EMAC_DSC_FLAG_SOP 0x80000000u define EMAC_DSC_FLAG_EOP 0x40000000u define EMAC_DSC_FLAG_OWNER 0x20000000u define EMAC_DSC_FLAG_EOQ ...

Page 23: ... on byte 16 of the buffer The software application must set this value prior to adding the descriptor to the active transmit list This field is not altered by the EMAC Note that this value is only checked on the first descriptor of a given packet where the start of packet SOP flag is set It can not be used to specify the offset of subsequent packet fragments Also since the buffer pointer may point...

Page 24: ... application can use this bit to detect when the EMAC transmitter for the corresponding channel has halted This is useful when the application appends additional packet descriptors to a transmit queue list that is already owned by the EMAC Note that this flag is valid on EOP descriptors only 2 5 4 10 Teardown Complete TDOWNCMPLT Flag This flag is used when a transmit queue is being torn down or ab...

Page 25: ...r this pointer to point to a newly appended descriptor The EMAC will use the new pointer value and proceed to the next descriptor unless the pNext value has already been read In this latter case the receiver will halt the receive channel in question and the software application may restart it at that time The software can detect this case by checking for an end of queue EOQ condition flag on the u...

Page 26: ...IGNERROR 0x00040000u define EMAC_DSC_FLAG_CRCERROR 0x00020000u define EMAC_DSC_FLAG_NOMATCH 0x00010000u 2 5 5 3 Buffer Offset This 16 bit field must be initialized to zero by the software application before adding the descriptor to a receive queue Whether or not this field is updated depends on the setting of the RXBUFFEROFFSET register When the offset register is set to a non zero value the recei...

Page 27: ...ueue This bit is set by the EMAC on EOP descriptors 2 5 5 8 Ownership OWNER Flag When set this flag indicates that the descriptor is currently owned by the EMAC This flag is set by the software application before adding the descriptor to the receive descriptor queue This flag is cleared by the EMAC once it is finished with a given set of descriptors associated with a received packet The flag is up...

Page 28: ...he EMAC in the SOP buffer descriptor if the received packet is an EMAC control frame and was not discarded because the RXCMFEN bit was set in the RXMBPENABLE 2 5 5 17 Overrun Flag This flag is set by the EMAC in the SOP buffer descriptor if the received packet was aborted due to a receive overrun 2 5 5 18 Code Error CODEERROR Flag This flag is set by the EMAC in the SOP buffer descriptor if the re...

Page 29: ...o operate more independently of the CPU It also prevents memory underflow conditions when the EMAC issues read or write requests to descriptor memory Memory accesses to read or write the actual Ethernet packet data are protected by the EMAC s internal FIFOs A descriptor is a 16 byte memory structure that holds information about a single Ethernet packet buffer which may contain a full or partial Et...

Page 30: ...MAC at any given time The MDIO module is designed to allow almost transparent operation of the MDIO interface with little maintenance from the CPU The MDIO module continuously polls 32 MDIO addresses in order to enumerate all PHY devices in the system Once a PHY device has been detected the MDIO module reads the MDIO PHY link status register LINK to monitor the PHY link state Link change events ar...

Page 31: ...esponded and whether or not the PHY currently has a link Using this information allows the software application to quickly determine which MDIO address the PHY is using 2 7 1 3 Active PHY Monitoring Once a PHY candidate has been selected for use the MDIO module transparently monitors its link state by reading the MDIO PHY link status register LINK Link change events are stored on the MDIO device a...

Page 32: ... in ALIVE if the PHY responded to the read request The corresponding bit is set in LINK if the PHY responded and also is currently linked In addition any PHY register read transactions initiated by the application software using USERACCESSn causes ALIVE to be updated The USERPHYSELn is used to track the link status of the connected PHY address A change in the link status of the PHY being monitored...

Page 33: ...mpletion of the write operation can be determined by polling the GO bit in USERACCESSn for a 0 4 Completion of the operation sets the corresponding USERINTRAW bit 0 or 1 in the MDIO user command complete interrupt register USERINTRAW corresponding to USERACCESSn used If interrupts have been enabled on this bit using the MDIO user command complete interrupt mask set register USERINTMASKSET then the...

Page 34: ...PHY register reads does not follow the procedure outlined in Section 2 7 2 3 Since the MDIO PHY alive status register ALIVE is used to initially select a PHY it is assumed that the PHY is acknowledging read operations It is possible that a PHY could become inactive at a future point in time An example of this would be a PHY that can have its MDIO addresses changed while the system is running It is...

Page 35: ...iver The transmit path includes transmit DMA engine transmit FIFO and MAC transmitter Statistics logic State RAM Interrupt controller Control registers and logic Clock and reset logic Figure 11 EMAC Module Block Diagram 2 8 1 1 Receive DMA Engine The receive DMA engine is the interface between the receive FIFO and the system core It interfaces to the CPU through the bus arbiter in the EMAC control...

Page 36: ... Logic The clock and reset submodule generates all the EMAC clocks and resets For more details on reset capabilities see Section 2 14 1 2 8 2 EMAC Module Operational Overview After reset initialization and configuration the host may initiate transmit operations Transmit operations are initiated by host writes to the appropriate transmit channel head descriptor pointer contained in the state RAM bl...

Page 37: ...re classified based on the destination MAC address Each of the eight channels is assigned its own MAC address enabling the EMAC module to act like eight virtual MAC adapters Also specific types of frames can be sent to specific channels For example multicast broadcast or other promiscuous error etc can each be received on a specific receive channel queue The EMAC keeps track of 36 different statis...

Page 38: ...ion when the EMAC is operating in full duplex mode the FULLDUPLEX bit is set in MACCONTROL When receive flow control is enabled and triggered the EMAC transmits a pause frame to request that the sending station stop transmitting for the period indicated within the transmitted pause frame The EMAC transmits a pause frame to the reserved multicast address at the first available opportunity immediate...

Page 39: ...t is set Adaptive performance pacing introduces delays into the normal transmission of frames delaying transmission attempts between stations reducing the probability of collisions occurring during heavy traffic as indicated by frame deferrals and collisions thereby increasing the chance of successful transmission When a frame is deferred suffers a single collision multiple collisions or excessive...

Page 40: ...mediately is set to the new pause frame pause time value Any remaining pause time from the previous pause frame is discarded If the TXFLOWEN bit in MACCONTROL is cleared then the pause timer immediately expires The EMAC does not start the transmission of a new data frame any sooner than 512 bit times after a pause frame with a nonzero pause time has finished being received MII_RXDV going inactive ...

Page 41: ...cast destination address The RXBROADEN bit in the receive multicast broadcast promiscuous channel enable register RXMBPENABLE determines if broadcast frames are enabled or filtered If broadcast frames are enabled when set to 1 then they are copied to only a single channel selected by the RXBROADCH bit in RXMBPENABLE The RXMULTEN bit in RXMBPENABLE determines if hash matching multicast frames are e...

Page 42: ...e buffers for each enabled channel including unicast multicast broadcast and promiscuous if receive QOS or receive flow control is used Disabled channel free buffer values are do not cares During initialization the host should write the number of free buffers for each enabled channel to the appropriate receive channel n free buffer count registers RXnFREEBUFFER The EMAC decrements the appropriate ...

Page 43: ...it value The last two bytes are the first two CRC bytes If the frame length is 1521 there are 1518 bytes transferred to memory regardless of the RXPASSCRC bit value The last byte is the first CRC byte If the frame length is 1522 there are 1518 bytes transferred to memory The last byte is the last data byte 2 10 8 Promiscuous Receive Mode When the promiscuous receive mode is enabled by setting the ...

Page 44: ...mes are transferred 0 1 1 1 1 All nonaddress matching frames with and without errors transferred to promiscuous channel 1 X 0 0 0 Proper data frames transferred to address match channel 1 X 0 0 1 Proper undersized data frames transferred to address match channel 1 X 0 1 0 Proper data and control frames transferred to address match channel 1 X 0 1 1 Proper undersized data and control frames transfe...

Page 45: ...roadcast promiscuous channel enable register RXMBPENABLE affects overrun frame treatment Table 6 shows how the overrun condition is handled for the middle of frame overrun Table 6 Middle of Frame Overrun Treatment Address Match RXCAFEN RXCEFEN Middle of Frame Overrun Treatment 0 0 X Overrun frame filtered 0 1 0 Overrun frame filtered 0 1 1 As much frame data as possible is transferred to the promi...

Page 46: ...perations 2 11 2 Transmit Channel Teardown The host commands a transmit channel teardown by writing the channel number to the transmit teardown register TXTEARDOWN When a teardown command is issued to an enabled transmit channel the following occurs Any frame currently in transmission completes normally The TDOWNCMPLT flag is set in the next SOP buffer descriptor in the chain if there is one The c...

Page 47: ... the use of the transfer node priority allocation register available at the device level Latency to descriptor RAM is low because RAM is local to the EMAC as it is part of the EMAC control module 2 13 Transfer Node Priority The device contains a chip level master priority register that is used to set the priority of the transfer node used in issuing memory transfer requests to system memory Althou...

Page 48: ...ibility of the software to verify that there are no pending frames to be transferred After writing a 1 to the SOFTRESET bit it may be polled to determine if the reset has occurred If a 1 is read the reset has not yet occurred if a 0 is read then a reset has occurred After a software reset operation all the EMAC registers need to be reinitialized for proper data transmission including the FULLDUPLE...

Page 49: ... done through the CPU interrupt controller Once the interrupt is mapped to a CPU interrupt general masking and unmasking of interrupts to control reentrancy should be done at the chip level by manipulating the interrupt core enable mask registers 2 15 3 MDIO Module Initialization The MDIO module is used to initially configure and monitor one or more external PHY devices Other than initializing the...

Page 50: ...and receive filter low priority frame threshold register RXFILTERLOWTHRESH 7 Most device drivers open with no multicast addresses so clear the MAC address hash registers MACHASH1 and MACHASH2 to 0 8 Write the receive buffer offset register RXBUFFEROFFSET value typically zero 9 Initially clear all unicast channels by writing FFh to the receive unicast clear register RXUNICASTCLEAR If unicast is des...

Page 51: ...criptor address of the last processed buffer is compared to the data in the register written by the EMAC port address of last buffer descriptor used by the EMAC If the two values are not equal which means that the EMAC has transmitted more packets than the CPU has processed interrupts for the transmit packet completion interrupt signal remains asserted If the two values are equal which means that ...

Page 52: ...le after processing packets by writing the appropriate CnTX key to the EMAC End Of Interrupt Vector register MACEOIVECTOR See Section 5 12 for the acknowledge key values 2 16 1 3 Statistics Interrupt The statistics level interrupt STATPEND is issued when any statistics value is greater than or equal to 8000 0000h if enabled by setting the STATMASK bit in the MAC interrupt mask set register MACINTM...

Page 53: ...eshold interrupts are intended to give the host an indication that resources are running low for a particular channel s The applications software must acknowledge the EMAC control module after receiving threshold interrupts by writing the appropriate CnRXTHRESH key to the EMAC End Of Interrupt Vector MACEOIVECTOR See Section 5 12 for the acknowledge key values 2 16 2 MDIO Module Interrupt Events a...

Page 54: ...safe interrupt processing upon entry to the ISR the software application should disable interrupts using the EMAC control module registers CnRXTHRESHEN CnRXEN CnTXEN CnMISCEN and then reenable them upon leaving the ISR If any interrupt signals are active at that time this creates another rising edge on the interrupt signal going to the CPU interrupt controller thus triggering another interrupt The...

Page 55: ... their default value When powering up after a synchronized reset all the EMAC submodules need to be reinitialized before any data transmission can happen For more information on the use of the PSC see your device specific System Reference Guide 2 18 Emulation Considerations EMAC emulation control is implemented for compatibility with other peripherals The SOFT and FREE bits in the emulation contro...

Page 56: ...C2RXEN EMAC Control Module Interrupt Core 2 Receive Interrupt Section 3 5 Enable Register 38h C2TXEN EMAC Control Module Interrupt Core 2 Transmit Interrupt Section 3 6 Enable Register 3Ch C2MISCEN EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Section 3 7 Enable Register 40h C0RXTHRESHSTAT EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Section 3 8 Status Register 4...

Page 57: ...C Control Module Interrupt Core 2 Receive Interrupts Per Section 3 12 Millisecond Register 84h C2TXIMAX EMAC Control Module Interrupt Core 2 Transmit Interrupts Per Section 3 13 Millisecond Register 3 1 EMAC Control Module Revision ID Register REVID The EMAC control module revision ID register REVID is shown in Figure 12 and described in Table 9 Figure 12 EMAC Control Module Revision ID Register R...

Page 58: ...erved RESET R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 10 EMAC Control Module Software Reset Register SOFTRESET Bit Field Value Description 31 1 Reserved 0 Reserved 0 RESET Software reset bit for the EMAC Control Module Clears the interrupt status control registers and CPPI Ram on the clock cycle following a write of 1 0 No software reset 1 Perform a software reset 58 EM...

Page 59: ...CEEN Enable pacing for RX interrupt pulse generation on Interrupt Core 2 0 Pacing for RX interrupts on Core 2 disabled 1 Pacing for RX interrupts on Core 2 enabled 19 C1TXPACEEN Enable pacing for TX interrupt pulse generation on Interrupt Core 1 0 Pacing for TX interrupts on Core 1 disabled 1 Pacing for TX interrupts on Core 1 enabled 18 C1RXPACEEN Enable pacing for RX interrupt pulse generation o...

Page 60: ...disabled for RX Channel 6 1 CnRXTHRESHPULSE generation is enabled for RX Channel 6 5 RXCH5THRESHEN Enable CnRXTHRESHPULSE interrupt generation for RX Channel 5 0 CnRXTHRESHPULSE generation is disabled for RX Channel 5 1 CnRXTHRESHPULSE generation is enabled for RX Channel 5 4 RXCH4THRESHEN Enable CnRXTHRESHPULSE interrupt generation for RX Channel 4 0 CnRXTHRESHPULSE generation is disabled for RX ...

Page 61: ...for RX Channel 6 1 CnRXPULSE generation is enabled for RX Channel 6 5 RXCH5EN Enable CnRXPULSE interrupt generation for RX Channel 5 0 CnRXPULSE generation is disabled for RX Channel 5 1 CnRXPULSE generation is enabled for RX Channel 5 4 RXCH4EN Enable CnRXPULSE interrupt generation for RX Channel 4 0 CnRXPULSE generation is disabled for RX Channel 4 1 CnRXPULSE generation is enabled for RX Channe...

Page 62: ...d for TX Channel 6 1 CnTXPULSE generation is enabled for TX Channel 6 5 TXCH5EN Enable CnTXPULSE interrupt generation for TX Channel 5 0 CnTXPULSE generation is disabled for TX Channel 5 1 CnTXPULSE generation is enabled for TX Channel 5 4 TXCH4EN Enable CnTXPULSE interrupt generation for TX Channel 4 0 CnTXPULSE generation is disabled for TX Channel 4 1 CnTXPULSE generation is enabled for TX Chan...

Page 63: ...rrupts are generated 0 CnMISCPULSE generation is disabled for EMAC STATPEND interrupts 1 CnMISCPULSE generation is enabled for EMAC STATPEND interrupts 2 HOSTPENDEN Enable CnMISCPULSE interrupt generation when EMAC host interrupts are generated 0 CnMISCPULSE generation is disabled for EMAC HOSTPEND interrupts 1 CnMISCPULSE generation is enabled for EMAC HOSTPEND interrupts 1 LINKINT0EN Enable CnMI...

Page 64: ...tatus for RX Channel 5 masked by the CnRXTHRESHEN register 0 RX Channel 5 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt 1 RX Channel 5 satisfies conditions to generate a CnRXTHRESHPULSE interrupt 4 RXCH4THRESHSTAT Interrupt status for RX Channel 4 masked by the CnRXTHRESHEN register 0 RX Channel 4 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt 1 RX Channe...

Page 65: ...5 masked by the CnRXEN register 0 RX Channel 5 does not satisfy conditions to generate a CnRXPULSE interrupt 1 RX Channel 5 satisfies conditions to generate a CnRXPULSE interrupt 4 RXCH4STAT Interrupt status for RX Channel 4 masked by the CnRXEN register 0 RX Channel 4 does not satisfy conditions to generate a CnRXPULSE interrupt 1 RX Channel 4 satisfies conditions to generate a CnRXPULSE interrup...

Page 66: ...l 5 masked by the CnTXEN register 0 TX Channel 5 does not satisfy conditions to generate a CnTXPULSE interrupt 1 TX Channel 5 satisfies conditions to generate a CnTXPULSE interrupt 4 TXCH4STAT Interrupt status for TX Channel 4 masked by the CnTXEN register 0 TX Channel 4 does not satisfy conditions to generate a CnTXPULSE interrupt 1 TX Channel 4 satisfies conditions to generate a CnTXPULSE interr...

Page 67: ...ster 0 EMAC STATPEND does not satisfy conditions to generate a CnMISCPULSE interrupt 1 EMAC STATPEND satisfies conditions to generate a CnMISCPULSE interrupt 2 HOSTPENDSTAT Interrupt status for EMAC HOSTPEND masked by the CnMISCEN register 0 EMAC HOSTPEND does not satisfy conditions to generate a CnMISCPULSE interrupt 1 EMAC HOSTPEND satisfies conditions to generate a CnMISCPULSE interrupt 1 LINKI...

Page 68: ...er of CnRXPULSE interrupts generated per millisecond when CnRXPACEEN is enabled in INTCONTROL The pacing mechanism can be described by the following pseudo code while 1 interrupt_count 0 Count interrupts over a 1ms window for i 0 i INTCONTROL INTPRESCALE 250 i interrupt_count NEW_INTERRUPT_EVENTS if i INTCONTROL INTPRESCALE pace_counter BLOCK_EMAC_INTERRUPTS else ALLOW_EMAC_INTERRUPTS ALLOW_EMAC_I...

Page 69: ...mber of CnTXPULSE interrupts generated per millisecond when CnTXPACEEN is enabled in INTCONTROL The pacing mechanism can be described by the following pseudo code while 1 interrupt_count 0 Count interrupts over a 1ms window for i 0 i INTCONTROL INTPRESCALE 250 i interrupt_count NEW_INTERRUPT_EVENTS if i INTCONTROL INTPRESCALE pace_counter BLOCK_EMAC_INTERRUPTS else ALLOW_EMAC_INTERRUPTS ALLOW_EMAC...

Page 70: ...errupt Masked Register Section 4 8 28h USERINTMASKSET MDIO User Command Complete Interrupt Mask Set Register Section 4 9 2Ch USERINTMASKCLEAR MDIO User Command Complete Interrupt Mask Clear Register Section 4 10 80h USERACCESS0 MDIO User Access Register 0 Section 4 11 84h USERPHYSEL0 MDIO User PHY Select Register 0 Section 4 12 88h USERACCESS1 MDIO User Access Register 1 Section 4 13 8Ch USERPHYSE...

Page 71: ...nnel that is available in the module It is currently set to 1 This implies that MDIOUserAccess1 is the highest available user access channel 23 21 Reserved 0 Reserved 20 PREAMBLE Preamble disable 0 Standard MDIO preamble is used 1 Disables this device from sending MDIO frame preambles 19 FAULT Fault indicator This bit is set to 1 if the MDIO pins fail to read back what the device is driving onto t...

Page 72: ...0 has no effect 0 The PHY fails to acknowledge the access 1 The most recent access to the PHY with an address corresponding to the register bit number was acknowledged by the PHY 4 4 PHY Link Status Register LINK The PHY link status register LINK is shown in Figure 28 and described in Table 26 Figure 28 PHY Link Status Register LINK 31 0 LINK R 0 LEGEND R Read only n value after reset Table 26 PHY...

Page 73: ...es that there was an MDIO link change event that is change in the LINK register corresponding to the PHY address in USERPHYSEL1 Writing a 1 will clear the event writing a 0 has no effect 0 No MDIO link change event 1 An MDIO link change event change in the LINK register corresponding to the PHY address in MDIO user PHY select register USERPHYSEL1 0 USERPHY0 MDIO Link change event raw value When as...

Page 74: ... to the PHY address in USERPHYSEL1 and the corresponding LINKINTENB bit was set Writing a 1 will clear the event writing a 0 has no effect 0 No MDIO link change event 1 An MDIO link change event change in the LINK register corresponding to the PHY address in MDIO user PHY select register USERPHYSEL1 and the LINKINTENB bit in USERPHYSEL1 is set to 1 0 USERPHY0 MDIO Link change interrupt masked valu...

Page 75: ...mplete event bit When asserted the bit indicates that the previously scheduled PHY read or write command using the USERACCESS1 register has completed Writing a 1 will clear the event writing a 0 has no effect 0 No MDIO user command complete event 1 The previously scheduled PHY read or write command using MDIO user access register USERACCESS1 has completed 0 USERACCESS0 MDIO User command complete e...

Page 76: ...cheduled PHY read or write command using that particular USERACCESS1 register has completed Writing a 1 will clear the interrupt writing a 0 has no effect 0 No MDIO user command complete event 1 The previously scheduled PHY read or write command using MDIO user access register USERACCESS1 has completed and the corresponding bit in USERINTMASKSET is set to 1 0 USERACCESS0 Masked value of MDIO User ...

Page 77: ...mand complete interrupts for the USERACCESS1 register MDIO user interrupt for USERACCESS1 is disabled if the corresponding bit is 0 Writing a 0 to this bit has no effect 0 MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is disabled 1 MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is enabled 0 USERACCESS0 MDIO user interrupt m...

Page 78: ...complete interrupt mask clear for USERINTMASKED 1 Setting the bit to 1 will disable further user command complete interrupts for USERACCESS1 Writing a 0 to this bit has no effect 0 MDIO user command complete interrupts for the MDIO user access register USERACCESS1 is enabled 1 MDIO user command complete interrupts for the MDIO user access register USERACCESS1 is disabled 0 USERACCESS0 MDIO user co...

Page 79: ...iteable only if the MDIO state machine is enabled This bit will self clear when the requested access has been completed Any writes to USERACCESS0 are blocked when the GO bit is 1 30 WRITE Write enable bit Setting this bit to 1 causes the MDIO transaction to be a register write otherwise it is a register read 0 The user command is a read operation 1 The user command is a write operation 29 ACK 0 1 ...

Page 80: ...select bit Default value is 0 which implies that the link status is determined by the MDIO state machine This is the only option supported on this device 0 The link status is determined by the MDIO state machine 1 Not supported 6 LINKINTENB Link change interrupt enable Set to 1 to enable link change status interrupts for PHY address specified in PHYADRMON Link change interrupts are disabled if thi...

Page 81: ...eable only if the MDIO state machine is enabled This bit will self clear when the requested access has been completed Any writes to USERACCESS0 are blocked when the GO bit is 1 30 WRITE Write enable bit Setting this bit to 1 causes the MDIO transaction to be a register write otherwise it is a register read 0 The user command is a read operation 1 The user command is a write operation 29 ACK 0 1 Ac...

Page 82: ...ue is 0 which implies that the link status is determined by the MDIO state machine This is the only option supported on this device 0 The link status is determined by the MDIO state machine 1 Not supported 6 LINKINTENB Link change interrupt enable Set to 1 to enable link change status interrupts for the PHY address specified in PHYADRMON Link change interrupts are disabled if this bit is cleared t...

Page 83: ...scuous Channel Enable Register Section 5 21 104h RXUNICASTSET Receive Unicast Enable Set Register Section 5 22 108h RXUNICASTCLEAR Receive Unicast Clear Register Section 5 23 10Ch RXMAXLEN Receive Maximum Length Register Section 5 24 110h RXBUFFEROFFSET Receive Buffer Offset Register Section 5 25 114h RXFILTERLOWTHRESH Receive Filter Low Priority Frame Threshold Register Section 5 26 120h RX0FLOWT...

Page 84: ...Ch TX7HDP Transmit Channel 7 DMA Head Descriptor Pointer Register Section 5 46 620h RX0HDP Receive Channel 0 DMA Head Descriptor Pointer Register Section 5 47 624h RX1HDP Receive Channel 1 DMA Head Descriptor Pointer Register Section 5 47 628h RX2HDP Receive Channel 2 DMA Head Descriptor Pointer Register Section 5 47 62Ch RX3HDP Receive Channel 3 DMA Head Descriptor Pointer Register Section 5 47 6...

Page 85: ...244h TXDEFERRED Deferred Transmit Frames Register Section 5 50 18 248h TXCOLLISION Transmit Collision Frames Register Section 5 50 19 24Ch TXSINGLECOLL Transmit Single Collision Frames Register Section 5 50 20 250h TXMULTICOLL Transmit Multiple Collision Frames Register Section 5 50 21 254h TXEXCESSIVECOLL Transmit Excessive Collision Frames Register Section 5 50 22 258h TXLATECOLL Transmit Late C...

Page 86: ...C0 020Dh Current transmit revision value 5 2 Transmit Control Register TXCONTROL The transmit control register TXCONTROL is shown in Figure 40 and described in Table 39 Figure 40 Transmit Control Register TXCONTROL 31 16 Reserved R 0 15 1 0 Reserved TXEN R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 39 Transmit Control Register TXCONTROL Field Descriptions Bit Field Value D...

Page 87: ... Field Value Description 31 3 Reserved 0 Reserved 2 0 TXTDNCH 0 7h Transmit teardown channel The transmit channel teardown is commanded by writing the encoded value of the transmit channel to be torn down The teardown register is read as 0 0 Teardown transmit channel 0 1h Teardown transmit channel 1 2h Teardown transmit channel 2 3h Teardown transmit channel 3 4h Teardown transmit channel 4 5h Tea...

Page 88: ...4EC0 020Dh Current receive revision value 5 5 Receive Control Register RXCONTROL The receive control register RXCONTROL is shown in Figure 43 and described in Table 42 Figure 43 Receive Control Register RXCONTROL 31 16 Reserved R 0 15 1 0 Reserved RXEN R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 42 Receive Control Register RXCONTROL Field Descriptions Bit Field Value Desc...

Page 89: ... Bit Field Value Description 31 3 Reserved 0 Reserved 2 0 RXTDNCH 0 7h Receive teardown channel The receive channel teardown is commanded by writing the encoded value of the receive channel to be torn down The teardown register is read as 0 0 Teardown receive channel 0 1h Teardown receive channel 1 2h Teardown receive channel 2 3h Teardown receive channel 3 4h Teardown receive channel 4 5h Teardow...

Page 90: ...e 44 Transmit Interrupt Status Unmasked Register TXINTSTATRAW Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 TX7PEND 0 1 TX7PEND raw interrupt read before mask 6 TX6PEND 0 1 TX6PEND raw interrupt read before mask 5 TX5PEND 0 1 TX5PEND raw interrupt read before mask 4 TX4PEND 0 1 TX4PEND raw interrupt read before mask 3 TX3PEND 0 1 TX3PEND raw interrupt read before mask 2...

Page 91: ... R Read only n value after reset Table 45 Transmit Interrupt Status Masked Register TXINTSTATMASKED Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 TX7PEND 0 1 TX7PEND masked interrupt read 6 TX6PEND 0 1 TX6PEND masked interrupt read 5 TX5PEND 0 1 TX5PEND masked interrupt read 4 TX4PEND 0 1 TX4PEND masked interrupt read 3 TX3PEND 0 1 TX3PEND masked interrupt read 2 TX2PEN...

Page 92: ... enable interrupt a write of 0 has no effect 6 TX6MASK 0 1 Transmit channel 6 interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect 5 TX5MASK 0 1 Transmit channel 5 interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect 4 TX4MASK 0 1 Transmit channel 4 interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect 3 TX3MASK 0 1 Transmit...

Page 93: ... disable interrupt a write of 0 has no effect 6 TX6MASK 0 1 Transmit channel 6 interrupt mask clear bit Write 1 to disable interrupt a write of 0 has no effect 5 TX5MASK 0 1 Transmit channel 5 interrupt mask clear bit Write 1 to disable interrupt a write of 0 has no effect 4 TX4MASK 0 1 Transmit channel 4 interrupt mask clear bit Write 1 to disable interrupt a write of 0 has no effect 3 TX3MASK 0 ...

Page 94: ... Reserved 0 Reserved 27 STATPEND 0 1 EMAC module statistics interrupt STATPEND pending status bit 26 HOSTPEND 0 1 EMAC module host error interrupt HOSTPEND pending status bit 25 LINKINT0 0 1 MDIO module USERPHYSEL0 LINKINT0 status bit 24 USERINT0 0 1 MDIO module USERACCESS0 USERINT0 status bit 23 16 TXPEND 0 FFh Transmit channels 0 7 interrupt TXnPEND pending status Bit 16 is TX0PEND 15 8 RXTHRESH...

Page 95: ...TVECT 0 1Fh Acknowledge EMAC Control Module Interrupts 0h Acknowledge C0RXTHRESH Interrupt 1h Acknowledge C0RX Interrupt 2h Acknowledge C0TX Interrupt 3h Acknowledge C0MISC Interrupt STATPEND HOSTPEND MDIO LINKINT0 MDIO USERINT0 4h Acknowledge C1RXTHRESH Interrupt 5h Acknowledge C1RX Interrupt 6h Acknowledge C1TX Interrupt 7h Acknowledge C1MISC Interrupt STATPEND HOSTPEND MDIO LINKINT0 MDIO USERIN...

Page 96: ...fore mask 14 RX6THRESHPEND 0 1 RX6THRESHPEND raw interrupt read before mask 13 RX5THRESHPEND 0 1 RX5THRESHPEND raw interrupt read before mask 12 RX4THRESHPEND 0 1 RX4THRESHPEND raw interrupt read before mask 11 RX3THRESHPEND 0 1 RX3THRESHPEND raw interrupt read before mask 10 RX2THRESHPEND 0 1 RX2THRESHPEND raw interrupt read before mask 9 RX1THRESHPEND 0 1 RX1THRESHPEND raw interrupt read before ...

Page 97: ...served 0 Reserved 15 RX7THRESHPEND 0 1 RX7THRESHPEND masked interrupt read 14 RX6THRESHPEND 0 1 RX6THRESHPEND masked interrupt read 13 RX5THRESHPEND 0 1 RX5THRESHPEND masked interrupt read 12 RX4THRESHPEND 0 1 RX4THRESHPEND masked interrupt read 11 RX3THRESHPEND 0 1 RX3THRESHPEND masked interrupt read 10 RX2THRESHPEND 0 1 RX2THRESHPEND masked interrupt read 9 RX1THRESHPEND 0 1 RX1THRESHPEND masked...

Page 98: ...mask set bit Write 1 to enable interrupt a write of 0 has no effect 11 RX3THRESHMASK 0 1 Receive channel 3 threshold mask set bit Write 1 to enable interrupt a write of 0 has no effect 10 RX2THRESHMASK 0 1 Receive channel 2 threshold mask set bit Write 1 to enable interrupt a write of 0 has no effect 9 RX1THRESHMASK 0 1 Receive channel 1 threshold mask set bit Write 1 to enable interrupt a write o...

Page 99: ...lear bit Write 1 to disable interrupt a write of 0 has no effect 11 RX3THRESHMASK 0 1 Receive channel 3 threshold mask clear bit Write 1 to disable interrupt a write of 0 has no effect 10 RX2THRESHMASK 0 1 Receive channel 2 threshold mask clear bit Write 1 to disable interrupt a write of 0 has no effect 9 RX1THRESHMASK 0 1 Receive channel 1 threshold mask clear bit Write 1 to disable interrupt a w...

Page 100: ...1 Statistics pending interrupt STATPEND raw interrupt read before mask 5 18 MAC Interrupt Status Masked Register MACINTSTATMASKED The MAC interrupt status masked register MACINTSTATMASKED is shown in Figure 56 and described in Table 55 Figure 56 MAC Interrupt Status Masked Register MACINTSTATMASKED 31 16 Reserved R 0 15 2 1 0 Reserved HOSTPEND STATPEND R 0 R 0 R 0 LEGEND R Read only n value after ...

Page 101: ...te 1 to enable interrupt a write of 0 has no effect 5 20 MAC Interrupt Mask Clear Register MACINTMASKCLEAR The MAC interrupt mask clear register MACINTMASKCLEAR is shown in Figure 58 and described in Table 57 Figure 58 MAC Interrupt Mask Clear Register MACINTMASKCLEAR 31 16 Reserved R 0 15 2 1 0 Reserved HOSTMASK STATMASK R 0 R W1C 0 R W1C 0 LEGEND R W Read Write R Read only W1C Write 1 to clear w...

Page 102: ... enabled 28 RXNOCHAIN Receive no buffer chaining bit 0 Received frames can span multiple buffers 1 The Receive DMA controller transfers each frame into a single buffer regardless of the frame or buffer size All remaining frame data after the first buffer is discarded The buffer descriptor buffer length field will contain the entire frame byte count up to 65535 bytes 27 25 Reserved 0 Reserved 24 RX...

Page 103: ... to receive promiscuous frames 4h Select channel 4 to receive promiscuous frames 5h Select channel 5 to receive promiscuous frames 6h Select channel 6 to receive promiscuous frames 7h Select channel 7 to receive promiscuous frames 15 14 Reserved 0 Reserved 13 RXBROADEN Receive broadcast enable Enable received broadcast frames to be copied to the channel selected by RXBROADCH bits 0 Broadcast frame...

Page 104: ...ulticast frames 1h Select channel 1 to receive multicast frames 2h Select channel 2 to receive multicast frames 3h Select channel 3 to receive multicast frames 4h Select channel 4 to receive multicast frames 5h Select channel 5 to receive multicast frames 6h Select channel 6 to receive multicast frames 7h Select channel 7 to receive multicast frames 104 EMAC MDIO Module SPRUFL5B April 2011 Submit ...

Page 105: ...ect May be read 6 RXCH6EN 0 1 Receive channel 6 unicast enable set bit Write 1 to set the enable a write of 0 has no effect May be read 5 RXCH5EN 0 1 Receive channel 5 unicast enable set bit Write 1 to set the enable a write of 0 has no effect May be read 4 RXCH4EN 0 1 Receive channel 4 unicast enable set bit Write 1 to set the enable a write of 0 has no effect May be read 3 RXCH3EN 0 1 Receive ch...

Page 106: ... enable a write of 0 has no effect 6 RXCH6EN 0 1 Receive channel 6 unicast enable clear bit Write 1 to clear the enable a write of 0 has no effect 5 RXCH5EN 0 1 Receive channel 5 unicast enable clear bit Write 1 to clear the enable a write of 0 has no effect 4 RXCH4EN 0 1 Receive channel 4 unicast enable clear bit Write 1 to clear the enable a write of 0 has no effect 3 RXCH3EN 0 1 Receive channel...

Page 107: ... buffer offset register RXBUFFEROFFSET is shown in Figure 63 and described in Table 62 Figure 63 Receive Buffer Offset Register RXBUFFEROFFSET 31 16 Reserved R 0 15 0 RXBUFFEROFFSET R W 0 LEGEND R W Read Write R Read only n value after reset Table 62 Receive Buffer Offset Register RXBUFFEROFFSET Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 0 RXBUFFEROFFSET 0 FFFFh Re...

Page 108: ...for filtering low priority incoming frames This field should remain 0 if no filtering is desired 5 27 Receive Channel Flow Control Threshold Registers RX0FLOWTHRESH RX7FLOWTHRESH The receive channel 0 7 flow control threshold register RXnFLOWTHRESH is shown in Figure 65 and described in Table 64 Figure 65 Receive Channel n Flow Control Threshold Register RXnFLOWTHRESH 31 16 Reserved R 0 15 8 7 0 R...

Page 109: ... free buffers available The RXFILTERTHRESH value is compared with this field to determine if low priority frames should be filtered The RXnFLOWTHRESH value is compared with this field to determine if receive flow control should be issued against incoming packets if enabled This is a write to increment field This field rolls over to 0 on overflow If hardware flow control or QOS is used the host mus...

Page 110: ...ird word to any receive buffer descriptor 13 RXOWNERSHIP Receive ownership write bit value 0 The EMAC writes the Receive ownership bit to 0 at the end of packet processing 1 The EMAC writes the Receive ownership bit to 1 at the end of packet processing If you do not use the ownership mechanism you can set this mode to preclude the necessity of software having to set this bit each time the buffer d...

Page 111: ...eive buffer flow control enable bit 0 Receive flow control is disabled Half duplex mode no flow control generated collisions are sent Full duplex mode no outgoing pause frames are sent 1 Receive flow control is enabled Half duplex mode collisions are initiated when receive buffer flow control is triggered Full duplex mode outgoing pause frames are sent when receive flow control is triggered 2 Rese...

Page 112: ... interrupts require hardware reset in order to recover A 0 packet length is an error but it is not detected 0 No error 1h SOP error the buffer is the first buffer in a packet but the SOP bit is not set in software 2h Ownership bit not set in SOP buffer 3h Zero next buffer descriptor pointer without EOP 4h Zero buffer pointer 5h Zero buffer length 6h Packet length error sum of buffers is less than ...

Page 113: ... The host error occurred on receive channel 6 7h The host error occurred on receive channel 7 7 3 Reserved 0 Reserved 2 RXQOSACT Receive Quality of Service QOS active bit When asserted indicates that receive quality of service is enabled and that at least one channel freebuffer count RXnFREEBUFFER is less than or equal to the RXFILTERLOWTHRESH value 0 Receive quality of service is disabled 1 Recei...

Page 114: ...halt SOFT bit determines operation of EMAC 1 Free running mode is enabled During emulation halt EMAC continues to operate 5 32 FIFO Control Register FIFOCONTROL The FIFO control register FIFOCONTROL is shown in Figure 70 and described in Table 69 Figure 70 FIFO Control Register FIFOCONTROL 31 16 Reserved R 0 15 2 1 0 Reserved TXCELLTHRESH R 0 R W 2h LEGEND R W Read Write R Read only n value after ...

Page 115: ...gister SOFTRESET The soft reset register SOFTRESET is shown in Figure 72 and described in Table 71 Figure 72 Soft Reset Register SOFTRESET 31 16 Reserved R 0 15 1 0 Reserved SOFTRESET R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 71 Soft Reset Register SOFTRESET Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 SOFTRESET Software reset Writing a 1 to...

Page 116: ... 5 36 MAC Source Address High Bytes Register MACSRCADDRHI The MAC source address high bytes register MACSRCADDRHI is shown in Figure 74 and described in Table 73 Figure 74 MAC Source Address High Bytes Register MACSRCADDRHI 31 24 23 16 MACSRCADDR2 MACSRCADDR3 R W 0 R W 0 15 8 7 0 MACSRCADDR4 MACSRCADDR5 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 73 MAC Source Address H...

Page 117: ...d be accepted or not The MAC hash address register 1 MACHASH1 is shown in Figure 75 and described in Table 74 Figure 75 MAC Hash Address Register 1 MACHASH1 31 0 MACHASH1 R W 0 LEGEND R W Read Write n value after reset Table 74 MAC Hash Address Register 1 MACHASH1 Field Descriptions Bit Field Value Description 31 0 MACHASH1 0 FFFF FFFFh Least significant 32 bits of the hash table corresponding to ...

Page 118: ...emented by one for each slot time after the collision 5 40 Transmit Pacing Algorithm Test Register TPACETEST The transmit pacing algorithm test register TPACETEST is shown in Figure 78 and described in Table 77 Figure 78 Transmit Pacing Algorithm Test Register TPACETEST 31 16 Reserved R 0 15 5 4 0 Reserved PACEVAL R 0 R 0 LEGEND R Read only n value after reset Table 77 Transmit Pacing Algorithm Te...

Page 119: ...the receive pause timer decrements to 0 then another outgoing pause frame is sent and the load decrement process is repeated 5 42 Transmit Pause Timer Register TXPAUSE The transmit pause timer register TXPAUSE is shown in Figure 80 and described in Table 79 Figure 80 Transmit Pause Timer Register TXPAUSE 31 16 Reserved R 0 15 0 PAUSETIMER R 0 LEGEND R Read only n value after reset Table 79 Transmi...

Page 120: ...bit should be cleared to zero for unused address channels 0 Address is not valid and will not be used for matching or filtering incoming packets 1 Address is valid and will be used for matching or filtering incoming packets 19 MATCHFILT Match or filter bit 0 The address will be used if the VALID bit is set to filter incoming packet addresses 1 The address will be used if the VALID bit is set to ma...

Page 121: ...e address table 5 45 MAC Index Register MACINDEX The MAC index register MACINDEX is shown in Figure 83 and described in Table 82 Figure 83 MAC Index Register MACINDEX 31 16 Reserved R 0 15 3 2 0 Reserved MACINDEX R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 82 MAC Index Register MACINDEX Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 0 MACINDEX 0...

Page 122: ...eset Host software must initialize these locations to 0 on reset 5 47 Receive Channel DMA Head Descriptor Pointer Registers RX0HDP RX7HDP The receive channel 0 7 DMA head descriptor pointer register RXnHDP is shown in Figure 85 and described in Table 84 Figure 85 Receive Channel n DMA Head Descriptor Pointer Register RXnHDP 31 0 RXnHDP R W x LEGEND R W Read Write n value after reset x value is ind...

Page 123: ...e value written to determine if the interrupt should be deasserted 5 49 Receive Channel Completion Pointer Registers RX0CP RX7CP The receive channel 0 7 completion pointer register RXnCP is shown in Figure 87 and described in Table 86 Figure 87 Receive Channel n Completion Pointer Register RXnCP 31 0 RXnCP R W x LEGEND R W Read Write n value after reset x value is indeterminate after reset Table 8...

Page 124: ... total number of good frames received on the EMAC A good frame is defined as having all of the following Any data or MAC control frame that matched a unicast broadcast or multicast address or matched due to promiscuous mode Was of length 64 to RXMAXLEN bytes inclusive Had no CRC error alignment error or code error See Section 2 5 5 for definitions of alignment code and CRC errors Overruns have no ...

Page 125: ... error is defined as having all of the following A frame containing an even number of nibbles Fails the frame check sequence test See Section 2 5 5 for definitions of alignment code and CRC errors Overruns have no effect on this statistic 5 50 6 Receive Alignment Code Errors Register RXALIGNCODEERRORS The total number of frames received on the EMAC that experienced an alignment error or code error...

Page 126: ...oadcast or multicast address or matched due to promiscuous mode Was less than 64 bytes long Had no CRC error alignment error or code error See Section 2 5 5 for definitions of alignment code and CRC errors Overruns have no effect on this statistic 5 50 10 Receive Frame Fragments Register RXFRAGMENTS The total number of frame fragments received on the EMAC A frame fragment is defined as having all ...

Page 127: ...nnel s corresponding free buffer register RXnFREEBUFFER value Was of length 64 to RXMAXLEN RXQOSEN bit is set in RXMBPENABLE Had no CRC error alignment error or code error See Section 2 5 5 for definitions of alignment code and CRC errors Overruns have no effect on this statistic 5 50 13 Receive Octet Frames Register RXOCTETS The total number of bytes in all good frames received on the EMAC A good...

Page 128: ...ause frames are always 64 byte multicast frames so appear in the multicast transmit frames register and 64 octect frames register statistics 5 50 18 Deferred Transmit Frames Register TXDEFERRED The total number of frames transmitted on the EMAC that first experienced deferment Such a frame is defined as having all of the following Was any data or MAC control frame destined for any unicast broadcas...

Page 129: ...wing Was any data or MAC control frame destined for any unicast broadcast or multicast address Was any size Had no carrier loss and no underrun Experienced 16 collisions before abandoning all attempts at transmitting the frame None of the collisions were late CRC errors have no effect on this statistic 5 50 23 Transmit Late Collision Frames Register TXLATECOLL The total number of frames when trans...

Page 130: ...e frame was being transmitted and experienced carrier loss that resulted in a frame of this size being transmitted then the frame is recorded in this statistic CRC errors alignment code errors and overruns do not affect the recording of frames in this statistic 5 50 28 Transmit and Receive 65 to 127 Octet Frames Register FRAME65T127 The total number of 65 byte to 127 byte frames received and trans...

Page 131: ...ed on the EMAC Such a frame is defined as having all of the following Any data or MAC control frame that was destined for any unicast broadcast or multicast address Did not experience late collisions excessive collisions underrun or carrier sense error Was 1024 bytes to RXMAXLEN bytes long CRC alignment code errors underruns and overruns do not affect frame recording in this statistic 5 50 33 Netw...

Page 132: ...or multicast address or matched due to promiscuous mode Was of any size including less than 64 byte and greater than RXMAXLEN byte frames The EMAC was unable to receive it because it did not have the resources to receive it cell FIFO full or no DMA buffer available after the frame was successfully started no SOF overrun CRC errors alignment errors and code errors have no effect on this statistic 5...

Page 133: ...x mode can only be used when all of the following are true The physical medium is capable of supporting simultaneous transmission and reception without interference There are exactly two stations connected with a full duplex point to point link As there is no contention for use of a shared medium the multiple access that is CSMA CD algorithms are unnecessary Both stations on the LAN are capable of...

Page 134: ...lds data rate in Mb s medium type maximum segment length 100m The definitions for the technologies mentioned in this document are in Table 87 Table 87 Physical Layer Definitions Term Definition 10Base T IEEE 802 3 Physical Layer specification for a 10 Mb s CSMA CD local area network over two pairs of twisted pair telephone wire 100Base T IEEE 802 3 Physical Layer specification for a 100 Mb s CSMA ...

Page 135: ...f this document Table 88 Document Revision History Reference Additions Modifications Deletions Figure 2 Changed figure Section 2 5 2 Changed first paragraph Section 2 5 3 Changed third paragraph 135 SPRUFL5B April 2011 Revision History Submit Documentation Feedback 2011 Texas Instruments Incorporated ...

Page 136: ...horized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge ...

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