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1.3

CPU Vector Table

Math tables

and functions

Bootloader

functions

Reset vector

CPU vector table

64 x 16

0x3F F000

0x3F FB50

0x3F FFFF

0x3F FFC0

Reset fetched from here when
VMAP=1
Other vectors fetched from here when
VMAP=1, ENPIE=0

CPU Vector Table

A CPU vector table resides in boot ROM memory from address 0x3F FFC0 - 0x3F FFFF. This vector table
is active after reset when VMAP = 1, ENPIE = 0 (PIE vector table disabled).

Figure 1-2. Vector Table Map

A

The VMAP bit is located in Status Register 1 (ST1). VMAP is always 1 on reset. It can be changed after reset by
software, however the normal operating mode will be to leave VMAP = 1.

B

The ENPIE bit is located in the PIECTRL register. The default state of this bit at reset is 0, which disables the
Peripheral Interrupt Expansion block (PIE).

The only vector that will normally be handled from the internal boot ROM memory is the reset vector
located at 0x3F FFC0. The reset vector is factory programmed to point to the InitBoot function stored in
the boot ROM. This function starts the boot load process. A series of checking operations is performed on
General Purpose I/O (GPIO I/O) pins to determine which boot mode to use. This boot mode selection is
described in

of this document.

The remaining vectors in the boot ROM are not used during normal operation. After the boot process is
complete, you should initialize the Peripheral Interrupt Expansion (PIE) vector table and enable the PIE
block. From that point on, all vectors, except reset, will be fetched from the PIE module and not the CPU
vector table shown in

14

Boot ROM Overview

SPRU722C – November 2004 – Revised October 2006

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Summary of Contents for TMS320*280 Series

Page 1: ...TMS320x280x 2801x 2804x Boot ROM Reference Guide Literature Number SPRU722C November 2004 Revised October 2006 ...

Page 2: ...2 SPRU722C November 2004 Revised October 2006 Submit Documentation Feedback ...

Page 3: ...rocedure 28 2 12 InitBoot Assembly Routine 29 2 13 SelectBootMode Function 30 2 14 CopyData Function 33 2 15 SCI_Boot Function 33 2 16 Parallel_Boot Function GPIO 35 2 17 SPI_Boot Function 40 2 18 I2C Boot Function 42 2 19 eCAN Boot Function 45 2 20 ExitBoot Assembly Routine 47 3 Building the Boot Table 49 3 1 The C2000 Hex Utility 50 3 2 Example Preparing a COFF File For eCAN Bootloading 51 4 Boo...

Page 4: ... 2 12 Overview of SCI_GetWordData Function 35 2 13 Overview of Parallel GPIO bootloader Operation 35 2 14 Parallel GPIO bootloader Handshake Protocol 36 2 15 Parallel GPIO Mode Overview 36 2 16 Parallel GPIO Mode Host Transfer Flow 37 2 17 16 Bit Parallel GetWord Function 38 2 18 8 Bit Parallel GetWord Function 39 2 19 SPI Loader 40 2 20 Data Transfer From EEPROM Flow 41 2 21 Overview of SPIA_GetW...

Page 5: ...ot Mode Selection 30 2 6 SPI 8 Bit Data Stream 40 2 7 I2C 8 Bit Data Stream 44 2 8 Bit Rate Values for Different XCLKIN Values 45 2 9 eCAN 8 Bit Data Stream 46 2 10 CPU Register Restored Values 48 3 1 Boot Loader Options 51 4 1 Bootloader Revision and Checksum Information 56 4 2 Bootloader Revision Per Device 56 A 1 Changes for Revision C 93 SPRU722C November 2004 Revised October 2006 List of Tabl...

Page 6: ...List of Tables 6 SPRU722C November 2004 Revised October 2006 Submit Documentation Feedback ...

Page 7: ... and its read write properties below A legend explains the notation used for the properties Reserved bits in a register figure designate a bit that is used for future device expansion Related Documentation From Texas Instruments The following documents describe the related devices and related support tools Copies of these documents are available on the Internet at www ti com Tip Enter the literatu...

Page 8: ...8xx 28xxx Inter Integrated Circuit I2C Reference Guide describes the features and operation of the inter integrated circuit I2C module that is available on the TMS320x280x digital signal processor DSP SPRU790 TMS320x28xx 28xxx Enhanced Quadrature Encoder Pulse eQEP Reference Guide describes the eQEP module which is used for interfacing with a linear or rotary incremental encoder to get position di...

Page 9: ...te how the eCAN module is set up for different modes of operation to help you come up to speed quickly in programming the eCAN All projects and CANalyzer configuration files are included in the attached SPRA876 zip file SPRA953 IC Package Thermal Metrics describes the traditional and new thermal metrics and will put their application in perspective with respect to system level junction temperature...

Page 10: ...www ti com Related Documentation From Texas Instruments Read This First 10 SPRU722C November 2004 Revised October 2006 Submit Documentation Feedback ...

Page 11: ...iew The boot ROM is a block of read only memory that is factory programmed Topic Page 1 1 Boot ROM Memory Map 12 1 2 On Chip Boot ROM IQ Math Tables 13 1 3 CPU Vector Table 14 SPRU722C November 2004 Revised October 2006 Boot ROM Overview 11 Submit Documentation Feedback ...

Page 12: ...sses 0x3F F000 0x3F FFF The on chip boot ROM is factory programmed with boot load routines and math tables for use with the C28x IQMath Library A Virtual Floating Point Engine literature number SPRC087 Chapter 4 contains the code for each of the following items Bootloader functions Version number release date and checksum Reset vector CPU vector table Used for test purposes only IQmath Tables Figu...

Page 13: ...ine Cosine Table Table size 1282 words Q format Q30 Contents 32 bit samples for one and a quarter period sine wave This is useful for accurate sine wave generation and 32 bit FFTs This can also be used for 16 bit math just skip over every second value Normalized Inverse Table Table size 528 words Q format Q29 Contents 32 bit normalized inverse samples plus saturation limits This table is used as a...

Page 14: ... disables the Peripheral Interrupt Expansion block PIE The only vector that will normally be handled from the internal boot ROM memory is the reset vector located at 0x3F FFC0 The reset vector is factory programmed to point to the InitBoot function stored in the boot ROM This function starts the boot load process A series of checking operations is performed on General Purpose I O GPIO I O pins to ...

Page 15: ... 0x3F FFEA 0x00 006A INT6 0x3F FFCC 0x00 004C USER3 0x3F FFEC 0x00 006C INT7 0x3F FFCE 0x00 004E USER4 0x3F FFEE 0x00 006E INT8 0x3F FFD0 0x00 0050 USER5 0x3F FFF0 0x00 0070 INT9 0x3F FFD2 0x00 0052 USER6 0x3F FFF2 0x00 0072 INT10 0x3F FFD4 0x00 0054 USER7 0x3F FFF4 0x00 0074 INT11 0x3F FFD6 0x00 0056 USER8 0x3F FFF6 0x00 0076 INT12 0x3F FFD8 0x00 0058 USER9 0x3F FFF8 0x00 0078 INT13 0x3F FFDA 0x0...

Page 16: ...www ti com CPU Vector Table Boot ROM Overview 16 SPRU722C November 2004 Revised October 2006 Submit Documentation Feedback ...

Page 17: ... Interrupt 20 2 6 Internal Pullup Resisters 20 2 7 PIE Configuration 20 2 8 Reserved Memory 20 2 9 Bootloader Modes 21 2 10 Bootloader Data Stream Structure 24 2 11 Basic Transfer Procedure 28 2 12 InitBoot Assembly Routine 29 2 13 SelectBootMode Function 30 2 14 CopyData Function 33 2 15 SCI_Boot Function 33 2 16 Parallel_Boot Function GPIO 35 2 17 SPI_Boot Function 40 2 18 I2 C Boot Function 42 ...

Page 18: ...n process as well as the specifics of each bootloader are described in the remainder of this document Figure 2 1 shows the basic bootloader flow Figure 2 1 Bootloader Flow Diagram The reset vector in boot ROM redirects program execution to the InitBoot function After performing device initialization the bootloader will check the state of GPIO pins to determine which boot mode you want to execute O...

Page 19: ...ion for Device Modes C2xLP Source C27x Mode Reset 28x Mode Compatible Mode OBJMODE 0 1 1 AMODE 0 0 1 PAGE0 0 0 0 M0M1MAP 1 1 1 1 Other Settings SXM 1 C 1 SPM 0 1 Normally for C27x compatibility the M0M1MAP would be 0 On these devices however it is tied off high internally therefore at reset M0M1MAP is always configured for 28x mode The boot ROM does not change the state of the PLL Note that the PL...

Page 20: ...articular device Each GPIO pin has an internal pullup resistor that can be enabled or disabled in software The pins that are read by the boot mode selection code to determine the boot mode selection have pull ups enabled after reset by default In noisy conditions it is still recommended that you configure each of the three boot mode selection pins externally The individual bootloaders SCI SPI eCAN...

Page 21: ...at address 0x50 on the 1 0 0 I2C bus eCAN A Boot 3 Call CAN_Boot to load from eCAN A mailbox 1 0 1 1 Boot to M0 SARAM 4 Jump to M0 SARAM address 0x00 0000 0 1 0 Boot to OTP 4 Jump to OTP address 0x3D 7800 0 0 1 Parallel I O Boot Load data from GPIO0 GPIO15 0 0 0 1 You must take extra care because of any effect toggling SPICLKA to select a boot mode may have on external logic 2 When booting directl...

Page 22: ... instruction in flash memory In this mode the boot ROM software will configure the device for 28x operation and then branch directly to location 0x3F 7FF6 in flash memory This location is just before the 128 bit code security module CSM password locations You are required to have previously programmed a branch instruction at location 0x3F 7FF6 that will redirect code execution to either a custom b...

Page 23: ... data into on chip memory from an external EEPROM via the SPI A port I2 C A boot mode I2 C A In this mode the boot ROM will load code and data into on chip memory from an external EEPROM at address 0x50 on the I2 C A bus The EEPROM must adhere to conventional I2 C EEPROM protocol with a 16 bit base address architecture eCAN Boot Mode eCAN A In this mode the eCAN A peripheral is used to transfer da...

Page 24: ...rved for future use and the bootloader simply reads the value and then discards it Currently only the SPI and I2 C bootloaders use these words to initialize registers The tenth and eleventh words comprise the 22 bit entry point address This address is used to initialize the PC after the boot load is complete This address is most likely the entry point of the program downloaded by the bootloader Th...

Page 25: ... If the block size is 0 this indicates the end of the source program Otherwise another section follows 13 Destination address of first block Addr 31 16 14 Destination address of first block Addr 15 0 15 First word of the first block in the source being loaded Last word of the first block of the source being loaded Block size of the 2nd block to load Destination address of second block Addr 31 16 D...

Page 26: ...02 0x0003 0x0004 0x0005 0002 0003 0004 0005 0002 0x0002 2nd block consists of 2 16 bit words 003F 0x003F8000 2nd block will be loaded starting at 0x3F8000 8000 7700 Data loaded 0x7700 0x7625 7625 0000 0x0000 Size of 0 indicates end of data stream After load has completed the following memory values will have been initialized as follows Location Value 0x3F9010 0x0001 0x3F9011 0x0002 0x3F9012 0x0003...

Page 27: ...ws For example a block size of 0x000A would indicate 10 words or 20 bytes in the block 25 26 LSB MSW destination address first block Addr 23 16 MSB MSW destination address first block Addr 31 24 27 28 LSB LSW destination address first block Addr 7 0 MSB LSW destination address first block Addr 15 8 29 30 LSB First word of the first block being loaded MSB First word of the first block being loaded ...

Page 28: ...03 0x3F9013 0x0004 0x3F9014 0x0005 0x3F8000 0x7700 0x3F8001 0x7625 PC Begins execution at 0x3F8000 Figure 2 6 illustrates the basic process a bootloader uses to determine whether 8 bit or 16 bit data stream has been selected transfer that data and start program execution This process occurs after the bootloader finds the valid boot mode selected by the state of GPIO pins The loader first compares ...

Page 29: ...of the Code Security Module CSM password locations If the CSM passwords are erased all 0xFFFFs then this has the effect of unlocking the CSM Otherwise the CSM will remain locked and this dummy read of the password locations will have no effect This can be useful if you have a new device that you want to boot load After the dummy read of the CSM password locations the InitBoot routine calls the Sel...

Page 30: ...assumed that you have previously programmed a branch statement at 0x3F 7FF6 to redirect program flow as desired 3 On devices without an eCAN A module this mode is reserved and should not be used 4 When booting directly to OTP or MO it is assumed that you have previously programmed or loaded code starting at the entry point location For a boot mode to be selected the pins corresponding to the desir...

Page 31: ...e exiting the SelectBootMode routine will re enable the watchdog and reset its timer If a bootloader is not going to be called then the watchdog is left untouched When selecting a boot mode the pins should be pulled high or low through a weak pulldown or weak pull up such that the DSP can drive them to a new state when required For example if you wanted to boot from the SCI A one of the pins you p...

Page 32: ...on is just before the CSM password Direct branch to the M0 SARAM block Execute user custom boot loader or TI provided boot loader memory without using up main flash memory Bootloader selected SCI SPI or parallel will copy data from the external device to internal memory A section of the data read determines the EntryPoint for execution after the boot routines have completed Yes Yes Yes Yes Yes Yes...

Page 33: ...hen the CopyData function is called the correct port is accessed The flow of the CopyData function is shown in Figure 2 9 Figure 2 9 Overview of CopyData Function The SCI boot mode asynchronously transfers code from SCI A to internal memory This boot mode only supports an incoming 8 bit data stream and follows the same data flow as outlined in Example 2 2 Figure 2 10 Overview of SCI Bootloader Ope...

Page 34: ...t higher baud rates the slew rate of the incoming data bits can be effected by transceiver and connector performance While normal serial communications may work well this slew rate may limit reliable auto baud detection at higher baud rates typically beyond 100kbaud and cause the auto baud lock feature to fail To avoid this the following is recommended 1 Achieve a baud lock between the host and 28...

Page 35: ...ternal host device by polling driving the GPIO27 and GPIO26 lines The handshake protocol shown in Figure 2 14 must be used to successfully transfer each word via GPIO 15 0 This protocol is very robust and allows for a slower or faster host to communicate with the DSP If the 8 bit mode is selected two consecutive 8 bit words are read to form a single 16 bit word The most significant byte MSB is rea...

Page 36: ...to the DSP that data is ready by pulling the GPIO27 pin low 3 The DSP reads the data and signals the host that the read is complete by pulling GPIO26 high 4 The bootloader waits until the host acknowledges the DSP by pulling GPIO27 high 5 The DSP again indicates it is ready for more data by pulling the GPIO26 pin low This process is repeated for each data value to be sent Figure 2 15 shows an over...

Page 37: ...on the data size of the incoming data stream 16 bit data stream For an 16 bit data stream the function Parallel_GetWordData16bit is used This function reads all 16 bits at a time The flow of this function is shown in Figure 2 17 8 bit data stream For an 8 bit data stream the function Parallel_GetWordData8bit is used The 8 bit routine shown in Figure 2 18 discards the upper 8 bits of the first read...

Page 38: ...PIO27 0 No Yes GPIO 15 0 Read word of data from GPIO26 1 DSP ack read complete Host ack GPIO27 1 Yes No Return WordData Parallel_Boot Function GPIO Figure 2 17 16 Bit Parallel GetWord Function 38 Bootloader Features SPRU722C November 2004 Revised October 2006 Submit Documentation Feedback ...

Page 39: ... 1 DSP ack read complete GPIO26 1 ready Data GPIO27 0 Signal host that DSP GPIO26 0 is ready to read MSB A Read word from GPIO 15 0 discard the upper 8 bits MSB of data lower 8 bits Return WordData WordData MSB LSB No No No Yes Yes Yes Parallel_Boot Function GPIO Figure 2 18 8 Bit Parallel GetWord Function SPRU722C November 2004 Revised October 2006 Bootloader Features 39 Submit Documentation Feed...

Page 40: ...and mimic a serial SPI EEPROM Immediately after entering the SPI_Boot function the pin functions for the SPI pins are set to primary and the SPI is initialized The initialization is done at the slowest speed possible Once the SPI is initialized and the key value read you could specify a change in baud rate or low speed peripheral clock Table 2 6 SPI 8 Bit Data Stream Byte Contents 1 LSB AA KeyValu...

Page 41: ... 0x08AA The least significant byte of this word is the byte read first and the most significant byte is the next byte fetched This is true of all word transfers on the SPI If the key value does not match then the load is aborted and the entry point for the flash 0x3F 7FF6 is returned to the calling routine Step 6 The next 2 bytes fetched can be used to change the value of the low speed peripheral ...

Page 42: ...2 C EEPROM protocol as described in this section with a 16 bit base address architecture Figure 2 22 EEPROM Device at Address 0x50 If the download is to be performed from a device other than an EEPROM then that device must be set up to operate in the slave mode and mimic the I2 C EEPROM Immediately after entering the I2 C boot function the GPIO pins are configured for I2 C A operation and the I2 C...

Page 43: ...ock frequency to the device must be between 14 MHz and 24 MHz This input clock frequency will result in a default 7 MHz to 12 MHz system clock SYSCLKOUT By default the bootloader sets the I2CPSC prescale value to 0 so that the I2 C clock will not be divided down from SYSCLKOUT This results in an I2 C clock between 7 MHz and 12 MHz which meets the I2 C peripheral clocking specification The I2CPSC v...

Page 44: ...ord If a non acknowledgment is received during the data read messages the I2 C bus will hang Table 2 7 shows the 8 bit data stream used by the I2 C Table 2 7 I2 C 8 Bit Data Stream Byte Contents 1 LSB AA KeyValue for memory width 8 bits 2 MSB 08h KeyValue for memory width 8 bits 3 LSB I2CPSC 7 0 4 reserved 5 LSB I2CCLKH 7 0 6 MSB I2CCLKH 15 8 7 LSB I2CCLKL 7 0 8 MSB I2CCLKL 15 8 17 LSB Reserved fo...

Page 45: ...d bit rate is achieved for different XCLKIN values as shown in Table 2 8 Table 2 8 Bit Rate Values for Different XCLKIN Values XCLKIN SYSCLKOUT Bit Rate 40 MHz 20 MHz 1 Mbps 20 MHz 10 MHz 500 kbps 10 MHz 5 MHz 250 kbps 5 MHz 2 5 MHz 125 kbps The SYSCLKOUT values shown are the reset values with the default PLL setting The BRPreg and bit time values are hard coded to 1 and 10 respectively Mailbox 1 ...

Page 46: ...ess 0xaabbccdd nn mm Length of first section mmnn ff ee MSW part of 32 bit address eeff hh hh LSW part of 32 bit address gghh Starting address of first section 0xeeffgghh xx xx First word of first section xx xx Second word of first section xx xx Last word of first section nn mm Length of second section mmnn ff ee MSW part of 32 bit address eeff hh gg LSW part of 32 bit address gghh Starting addres...

Page 47: ...registers with one exception The OBJMODE bit in ST1 is left set so that the device remains configured for C28x operation This flow is detailed in the following diagram Figure 2 27 ExitBoot Procedure Flow The following CPU registers are restored to their default values ACC 0x0000 0000 RPC 0x0000 0000 P 0x0000 0000 XT 0x0000 0000 ST0 0x0000 ST1 0x0A0B XAR0 XAR7 0x0000 0000 After the ExitBoot routine...

Page 48: ...0 XAR0 XAR7 0x0000 0000 DP 0x0000 ST0 0x0000 15 10 OVC 0 ST1 0x0A0B 15 13 ARP 0 9 7 PM 0 12 XF 0 6 V 0 11 M0M1MAP 1 5 N 0 10 reserved 4 Z 0 9 OBJMODE 1 3 C 0 8 AMODE 0 2 TC 0 7 IDLESTAT 0 1 OVM 0 6 EALLOW 0 0 SXM 0 5 LOOP 0 4 SPA 0 3 VMAP 1 2 PAGE0 0 1 DBGM 1 0 INTM 1 Bootloader Features 48 SPRU722C November 2004 Revised October 2006 Submit Documentation Feedback ...

Page 49: ...pter explains how to generate the data stream and boot table required for the bootloader Topic Page 3 1 The C2000 Hex Utility 50 3 2 Example Preparing a COFF File For eCAN Bootloading 51 SPRU722C November 2004 Revised October 2006 Building the Boot Table 49 Submit Documentation Feedback ...

Page 50: ... file is used by the linker to allocate the code sections to different memory blocks Each block of the boot table data corresponds to an initialized section in the COFF file Uninitialized sections are not converted by the hex conversion utility The following options may be useful The linker m option can be used to generate a map file This map file will show all of the sections that were created th...

Page 51: ...prior to reading data from the EEPROM i2cclkl value Specify the value for the I2CCLKL register This value will be loaded and take effect after all I2C options are loaded prior to reading data from the EEPROM This section shows how to convert a COFF file into a format suitable for CAN based bootloading This example assumes that the host sending the data stream is capable of reading an ASCII hex for...

Page 52: ...ata The HEX2000 exe utility can be used to convert the COFF file into a format that includes this boot information The following command syntax has been used to convert the application into an ASCII hex format file that includes all of the required information for the bootloader Example 3 2 HEX2000 exe Command Syntax C HEX2000 GPIO34TOG OUT boot gpio8 a Where boot Convert all sections into bootabl...

Page 53: ...5 01 Load 0x0155 words text section 3F 00 00 A0 Load block starting at 0x003FA000 AD 28 00 04 69 FF 1F 56 16 56 1A 56 40 Data 0x28AD 0x4000 etc 29 1F 76 00 00 02 29 1B 76 22 76 A9 28 18 00 A8 28 00 00 01 09 1D 61 C0 76 18 00 04 29 0F 6F 00 9B A9 24 01 DF 04 6C 04 29 A8 24 01 DF A6 1E A1 F7 86 24 A7 06 FC 63 E6 6F 19 00 Load 0x0019 words cinit section 00 00 18 00 Load block starting at 0x000018 FF ...

Page 54: ...www ti com Example Preparing a COFF File For eCAN Bootloading Building the Boot Table 54 SPRU722C November 2004 Revised October 2006 Submit Documentation Feedback ...

Page 55: ...on the Boot ROM version checksum and code Topic Page 4 1 Boot ROM Version and Checksum Information 56 4 2 Bootloader Code Revision History 56 4 3 Bootloader Code Listing V3 0 57 4 4 Bootloader Code Listing V4 0 87 SPRU722C November 2004 Revised October 2006 Bootloader Code Overview 55 Submit Documentation Feedback ...

Page 56: ...addition a zip file with each revision of the boot ROM code can be downloaded from the TI website at the same location as this document Table 4 2 Bootloader Revision Per Device Device s Silicon REVID Boot ROM Revision Address 0x883 F2808 F2806 0 First silicon Version 1 F2802 F2801 F2808 F2806 1 Rev A Version 2 F2802 F2801 F2808 F2806 2 Rev B and later Version 3 F2802 F2801 C2802 C2801 0 First sili...

Page 57: ...se the boot ROM software will loop in the autobaud lock function indefinitely Should the SCI A boot complete the user s software must check for a missing clock status and take the appropriate action Boot to eCAN A will not be taken Instead the boot ROM will loop indefinitely Version 1 Released August 2004 The initial release of the 280x boot ROM This version has the following known issues The eCAN...

Page 58: ...RD_LOCATION 0x3F7FF8 define ERROR 1 define NO_ERROR 0 define EIGHT_BIT 8 define SIXTEEN_BIT 16 define EIGHT_BIT_HEADER 0x08AA define SIXTEEN_BIT_HEADER 0x10AA typedef Uint16 uint16fptr extern uint16fptr GetWordData endif end of F280x_BOOT_H definition 58 Bootloader Code Overview SPRU722C November 2004 Revised October 2006 Submit Documentation Feedback ...

Page 59: ...cant 32 bits sect InitBoot _InitBoot This function performs the initial boot routine for the boot ROM This module performs the following actions 1 Initializes the stack pointer 2 Sets the device for C28x operating mode 3 Calls the main boot functions 4 Calls an exit routine _InitBoot Initialize the stack pointer __stack usect stack 0 MOV SP __stack Initialize the stack pointer Initialize the devic...

Page 60: ...ry point 3 Clear all XARn registers 4 Clear ACC P and XT registers 5 LRETR this will also clear the RPC register since 0 was on the stack _ExitBoot Insure that the stack is deallocated MOV SP __stack Clear the bottom of the stack This will end up in RPC when you are finished MOV SP 0 MOV SP 0 Load RPC with the entry point as determined by the boot mode This address will be returned in the ACC regi...

Page 61: ...x object operating mode ST0 0x0000 ST1 0x0A0B 15 10 OVC 0 15 13 ARP 0 9 7 PM 0 12 XF 0 6 V 0 11 M0M1MAP 1 5 N 0 10 reserved 4 Z 0 9 OBJMODE 1 3 C 0 8 AMODE 0 2 TC 0 7 IDLESTAT 0 1 OVM 0 6 EALLOW 0 0 SXM 0 5 LOOP 0 4 SPA 0 3 VMAP 1 2 PAGE0 0 1 DBGM 1 0 INTM 1 MOV SP 0 MOV SP 0x0A0B POP ST1 POP ST0 Jump to the EntryAddr as defined by the boot mode selected and continue execution LRETR eof SPRU722C N...

Page 62: ...IO34 SPICLKA SCITXDA SCITXB Flash 1 1 1 SCI 1 1 0 SPI 1 0 1 I2C 1 0 0 ECAN 0 1 1 RAM 0 1 0 OTP 0 0 1 I 0 0 0 0 define FLASH_BOOT 7 define SCI_BOOT 6 define SPI_BOOT 5 define I2C_BOOT 4 define CAN_BOOT 3 define RAM_BOOT 2 define OTP_BOOT 1 define PARALLEL_BOOT 0 Uint32 SelectBootMode Uint32 EntryAddr Uint16 BootMode EALLOW Set MUX for BOOT Select GpioCtrlRegs GPAMUX2 bit GPIO18 0 GpioCtrlRegs GPAMU...

Page 63: ... FLASH_ENTRY_POINT if BootMode RAM_BOOT return RAM_ENTRY_POINT if BootMode OTP_BOOT return OTP_ENTRY_POINT Otherwise disable the watchdog and check for the other boot modes that requre loaders EALLOW SysCtrlRegs WDCR 0x0068 EDIS if BootMode SCI_BOOT EntryAddr SCI_Boot else if BootMode SPI_BOOT EntryAddr SPI_Boot else if BootMode I2C_BOOT EntryAddr I2C_Boot else if BootMode CAN_BOOT EntryAddr CAN_B...

Page 64: ...Release Date include DSP280x_Device h This module disables the watchdog timer void WatchDogDisable EALLOW SysCtrlRegs WDCR 0x0068 Disable watchdog module EDIS This module enables the watchdog timer void WatchDogEnable EALLOW SysCtrlRegs WDCR 0x0028 Enable watchdog module SysCtrlRegs WDKEY 0x55 Clear the WD counter SysCtrlRegs WDKEY 0xAA EDIS EOF 64 Bootloader Code Overview SPRU722C November 2004 R...

Page 65: ...opyData void This routine copies multiple blocks of data from the host to the specified RAM locations There is no error checking on any of the destination addresses That is it is assumed all addresses and block size values are correct Multiple blocks of data are copied until a block size of 00 00 is encountered void CopyData struct HEADER Uint16 BlockSize Uint32 DestAddr BlockHeader Uint16 wordDat...

Page 66: ...e 32 bit value longData Uint32 GetWordData 16 Fetch the lower of the 32 bit value longData Uint32 GetWordData return longData void Read_ReservedFn void This function reads 8 reserved words in the header None of these reserved words are used by the this boot loader at this time they may be used in future devices for enhancements Loaders that use these words use their own read function void ReadRese...

Page 67: ... is the main SPI boot routine It will load code via the SPI A port It will return a entry point address back to the ExitBoot routine Uint32 SPI_Boot Uint32 EntryAddr Assign GetWordData to the SPI A version of the function GetWordData is a pointer to a function GetWordData SPIA_GetWordData 1 Init SPI A and set EEPROM chip enable low SPIA_Init 2 Enable EEPROM and send EEPROM Read Command SPIA_Transm...

Page 68: ...I SPICLK pins Enable pull ups on SPISIMO SPISOMI SPICLK SPISTE pins GpioCtrlRegs GPAPUD bit GPIO16 0 GpioCtrlRegs GPAPUD bit GPIO17 0 GpioCtrlRegs GPAPUD bit GPIO18 0 GpioCtrlRegs GPAPUD bit GPIO19 0 GpioCtrlRegs GPAPUD all 0xFFF0FFFF GpioCtrlRegs GPAMUX2 bit GPIO16 1 GpioCtrlRegs GPAMUX2 bit GPIO17 1 GpioCtrlRegs GPAMUX2 bit GPIO18 1 GpioCtrlRegs GPAMUX2 all 0x00000015 SPI A pins are asynch GpioC...

Page 69: ...ds are read and discarded and then returns to the main routine inline void SPIA_ReservedFn Uint16 speedData Uint16 I update LOSPCP register speedData SPIA_Transmit Uint16 0x0000 EALLOW SysCtrlRegs LOSPCP all speedData EDIS asm RPT 0x0F NOP update SPIBRR register speedData SPIA_Transmit Uint16 0x0000 SpiaRegs SPIBRR speedData asm RPT 0x0F NOP Read and discard the next 7 reserved words for I 1 I 7 I...

Page 70: ...www ti com Bootloader Code Listing V3 0 return wordData 70 Bootloader Code Overview SPRU722C November 2004 Revised October 2006 Submit Documentation Feedback ...

Page 71: ...32 GetLongData void extern void ReadReservedFn void Uint32 SCI_Boot void This module is the main SCI boot routine It will load code via the SCI A port It will return a entry point address back to the InitBoot routine which in turn calls the ExitBoot routine Uint32 SCI_Boot Uint32 EntryAddr Assign GetWordData to the SCI A version of the function GetWordData is a pointer to a function GetWordData SC...

Page 72: ...pioCtrlRegs GPAPUD bit GPIO29 0 GpioCtrlRegs GPAPUD all 0xCFFFFFFF Enable the SCI A pins GpioCtrlRegs GPAMUX2 bit GPIO28 1 GpioCtrlRegs GPAMUX2 bit GPIO29 1 GpioCtrlRegs GPAMUX2 all 0x05000000 Input qual for SCI A RX is asynch GpioCtrlRegs GPAQSEL2 bit GPIO28 3 EDIS return void SCIA_AutobaudLock void Perform autobaud lock with the host Note that if autobaud never occurs the program will hang in th...

Page 73: ...host is sending the data in the order LSB followed by MSB Uint16 SCIA_GetWordData Uint16 wordData Uint16 byteData wordData 0x0000 byteData 0x0000 Fetch the LSB and verify back to the host while SciaRegs SCIRXST bit RXRDY 1 wordData Uint16 SciaRegs SCIRXBUF bit RXDT SciaRegs SCITXBUF wordData Fetch the MSB and verify back to the host while SciaRegs SCIRXST bit RXRDY 1 byteData Uint16 SciaRegs SCIRX...

Page 74: ...unction definitions extern void CopyData void extern Uint32 GetLongData void extern void ReadReservedFn void define HOST_CTRL GPIO27 GPIO27 is the host control signal define DSP_CTRL GPIO26 GPIO26 is the DSP s control signal define HOST_DATA_NOT_RDY GpioDataRegs GPADAT bit HOST_CTRL 0 define WAIT_HOST_ACK GpioDataRegs GPADAT bit HOST_CTRL 1 Set DSP_ACK or Clear DSP_RDY GPIO 17 define DSP_ACK GpioD...

Page 75: ...14 0 GpioCtrlRegs GPAPUD bit GPIO13 0 GpioCtrlRegs GPAPUD bit GPIO12 0 GpioCtrlRegs GPAPUD bit GPIO11 0 GpioCtrlRegs GPAPUD bit GPIO10 0 GpioCtrlRegs GPAPUD bit GPIO9 0 GpioCtrlRegs GPAPUD bit GPIO8 0 GpioCtrlRegs GPAPUD bit GPIO7 0 GpioCtrlRegs GPAPUD bit GPIO6 0 GpioCtrlRegs GPAPUD bit GPIO5 0 GpioCtrlRegs GPAPUD bit GPIO4 0 GpioCtrlRegs GPAPUD bit GPIO3 0 GpioCtrlRegs GPAPUD bit GPIO2 0 GpioCtr...

Page 76: ...t mode Call Parallel_GetWordData with 16 bit mode so you only fetch the MSB of the KeyValue and not two bytes You will ignore the upper 8 bits and combine the result with the previous byte to form the header KeyValue wordData wordData 0x00FF wordData Parallel_GetWordData_16bit 8 if wordData EIGHT_BIT_HEADER Assign GetWordData to the parallel 8bit version of the function GetWordData is a pointer to...

Page 77: ...dData Uint16 Parallel_GetWordData_16bit Uint16 wordData Get a word of data If you are in 16 bit mode then you are done Parallel_WaitHostRdy wordData DATA Parallel_HostHandshake return wordData void Parallel_WaitHostRdy void This routine tells the host that the DSP is ready to receive data The DSP then waits for the host to signal that data is ready on the GP I O port e void Parallel_WaitHostRdy DS...

Page 78: ... this can cause the I2C to operate out of specification with a system clock between 7Mhz and 12Mhz The bit period prescalers I2CCLKH and I2CCLKL are configured to run the I2C at 50 duty cycle at 100kHz bit rate standard I2C mode when the system clock is 12Mhz These registers can be modified after receiving the first few bytes from the EEPROM see the boot rom documentation This allows the communica...

Page 79: ...eturn FLASH_ENTRY_POINT Check for clock and prescaler speed changes and reserved words I2C_ReservedFn Get point of entry address after load EntryAddr GetLongData Receive and copy one or more code sections to destination addresses CopyData return EntryAddr void I2C_Init void Initialize the I2C A port for communications with the host inline void I2C_Init void Configure I2C pins and turn on I2C clock...

Page 80: ...rror is returned inline Uint16 I2C_CheckKeyVal void To read a word from the EEPROM an address must be given first in master transmitter mode Then a restart is performed and data can be read back in master receiver mode I2caRegs I2CCNT 0x02 Setup how many bytes to send I2caRegs I2CDXR 0x00 Configure fifo data for byte I2caRegs I2CDXR 0x00 address of 0x0000 I2caRegs I2CMDR all 0x2620 Send data to se...

Page 81: ...l I2CPrescaler I2caRegs I2CMDR bit IRS 1 Read and discard the next 5 reserved words for I 1 I 5 I I2cClkHData I2C_GetWord return Uint16 I2C_GetWord void This routine fetches two bytes from the I2C A port and puts them together little endian style to form a single 16 bit value Uint16 I2C_GetWord void Uint16 LowByte I2caRegs I2CCNT 2 Setup how many bytes to expect I2caRegs I2CMDR all 0x2C20 Send sta...

Page 82: ..._Device h include 280x_Boot h Private functions void CAN_Init void Uint16 CAN_GetWordData void External functions extern void CopyData void extern Uint32 GetLongData void extern void ReadReservedFn void Uint32 CAN_Boot void This module is the main CAN boot routine It will load code via the CAN A port It will return a entry point address back to the InitBoot routine which in turn calls the ExitBoot...

Page 83: ...O regs GpioCtrlRegs GPAMUX2 bit GPIO30 1 GPIO30 is CANRXA GpioCtrlRegs GPAMUX2 bit GPIO31 1 GPIO31 is CANTXA Configure eCAN RX and TX pins for eCAN transmissions using eCAN regs ECanaRegs CANTIOC bit TXFUNC 1 ECanaRegs CANRIOC bit RXFUNC 1 Enable internal pullups for the CAN pins GpioCtrlRegs GPAPUD bit GPIO30 0 GpioCtrlRegs GPAPUD bit GPIO31 0 Asynch Qual GpioCtrlRegs GPAQSEL2 bit GPIO30 3 Initia...

Page 84: ...hile ECanaRegs CANES bit CCE 0 Wait for CCE bit to be cleared Disable all Mailboxes ECanaRegs CANME all 0 Required before writing the MSGIDs Assign MSGID to MBOX1 ECanaMboxes MBOX1 MSGID all 0x00040000 Configure MBOX1 to be a receive MBOX ECanaRegs CANMD all 0x0002 Enable MBOX1 ECanaRegs CANME all 0x0002 EDIS return Uint16 CAN_GetWordData void This routine fetches two bytes from the CAN A port and...

Page 85: ...rt of 8 reserved words stream 00 00 Part of 8 reserved words stream bb aa MS part of 32 bit address aabb dd cc LS part of 32 bit address ccdd Final Entry point address 0xaabbccdd nn mm Length of first section mm nn ff ee MS part of 32 bit address eeff hh gg LS part of 32 bit address gghh Entry point address of first section 0xeeffgghh xx xx First word of first section xx xx Second word xxx Last wo...

Page 86: ...tionship 3 Changed the statement ECanaMboxes MBOX1 MSGID bit STDMSGID 1 to ECanaMboxes MBOX1 MSGID all 0x00040000 since IDE AME bits are not initialized in the previous version 4 Employed Shadow writes to CANBTC register EOF 86 Bootloader Code Overview SPRU722C November 2004 Revised October 2006 Submit Documentation Feedback ...

Page 87: ...S origin 0x3FFFC0 length 0x000040 PAGE 1 EBSS origin 0x400 length 0x002 STACK origin 0x402 length 0x200 SECTIONS IQmathTables load TABLES PAGE 0 InitBoot load BOOT PAGE 0 text load BOOT PAGE 0 BootVecs load VECS PAGE 0 Checksum load CHECKSUM PAGE 0 Version load VERSION PAGE 0 stack load STACK PAGE 1 ebss load EBSS PAGE 1 rsvd1 load RSVD1 PAGE 0 This section only shows the code that was modified fr...

Page 88: ...inter 2 Sets the device for C28x operating mode 3 Calls the main boot functions 4 Calls an exit routine _InitBoot Initalize the stack pointer __stack usect stack 0 MOV SP __stack Initalize the stack pointer Initalize the device for running in C28x mode C28OBJ Select C28x object mode C28ADDR Select C27x C28x addressing C28MAP Set blocks M0 M1 for C28x mode CLRC PAGE0 Always use stack addressing mod...

Page 89: ...t the stack is deallocated MOV SP __stack Clear the bottom of the stack This will endup in RPC when we are finished MOV SP 0 MOV SP 0 Load RPC with the entry point as determined by the boot mode This address will be returned in the ACC register PUSH ACC POP RPC Put registers back in their reset state Clear all the XARn ACC XT and P and DP registers NOTE Leave the device in C28x operating mode OBJM...

Page 90: ...TM 1 MOV SP 0 MOV SP 0x0A0B POP ST1 POP ST0 Jump to the EntryAddr as defined by the boot mode selected and continue execution LRETR eof TI File Revision main 1 Checkin Date May 2 2006 21 10 16 FILE ITRAPIsr asm TITLE 280x Boot Rom ITRAP ISR Functions _ITRAPIsr Notes TI Release Release Date def _ITRAPIsr _ITRAPIsr This is the ITRAP interrupt service routine for thet boot ROM CPU vector table This r...

Page 91: ...boot loader functions InitBoot The rest of the vectors are populated for test purposes only TI Release Release Date The vector table located in boot ROM at 0x3F FFC0 0x3F FFFF will be filled with the following data Only the reset vector which points to the InitBoot routine will be used during normal operation The remaining vectors are set for internal testing purposes and will not be fetched from ...

Page 92: ...064 long _ITRAPIsr ITRAP long 0x000068 long 0x00006a long 0x00006c long 0x00006e long 0x000070 long 0x000072 long 0x000074 long 0x000076 long 0x000078 long 0x00007a long 0x00007c long 0x00007e 92 Bootloader Code Overview SPRU722C November 2004 Revised October 2006 Submit Documentation Feedback ...

Page 93: ... ROM version per device table Table 1 1 Updated the ITRAP vector information and added a note to the table to explain the change Section 2 5 Added this section to describe the behavior of the ITRAP vector within the CPU vector table Table 2 2 Added info for devices that do not have an eCAN A module Section 4 2 Inserted information for version 4 of the boot ROM code Section 4 1 Moved the version an...

Page 94: ...om TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alterati...

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