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I
2
C_Boot
Set CopyWord function
pointer to
I2C_CopyWord
Enable SDAA and
SCLA pins
Enable pullups on
SDAA and SCLA
Enable I2C−A clock
Set slave address 0x50
I
2
C prescaler I2CPSC=0
100-kHz bit rate at
12-MHz SYSCLKOUT
†
Enable TX/RX FIFOs to
receive 2 bytes
Place I
2
C in master
transmitter mode.
Set EEPROM address
pointer to 0x0000
NACK
received
?
Yes
Read KeyValue
No
Valid
KeyValue
(0x08AA)
?
Return
FLASH_ENTRY_POINT
Return
FLASH_ENTRY_POINT
No
Read I2CPSC value
Read I2CCLKH value
Read I2CCLKL value
Put I2C−A in Reset
Set I2CPSC value
Set I2CCLKH value
Set I2CCLKL value
Bring I2C−A out of Reset
Read and discard 5
reserved words
Yes
Read EntryPoint
address
Call CopyData
Return
EntryPoint
†
During device boot, SYSCLKOUT will be the device input frequency divided by two.
I
2
C Boot Function
Figure 2-23. Overview of I2C_Boot Function
To use the I
2
C-A bootloader, the input clock frequency to the device must be between 14 MHz and 24
MHz. This input clock frequency will result in a default 7 MHz to 12 MHz system clock (SYSCLKOUT). By
default, the bootloader sets the I2CPSC prescale value to 0 so that the I
2
C clock will not be divided down
from SYSCLKOUT. This results in an I
2
C clock between 7 MHz and 12 MHz, which meets the I
2
C
peripheral clocking specification. The I2CPSC value can be modified after receiving the first few bytes
from the EEPROM, but it is not advisable to do this, because this can cause the I
2
C to operate out of the
required specification.
The bit-period prescalers (I2CCLKH and I2CCLKL) are configured by the bootloader to run the I
2
C at a 50
percent duty cycle at 100-kHz bit rate (standard I
2
C mode) when the system clock is 12 MHz. These
registers can be modified after receiving the first few bytes from the EEPROM. This allows the
communication to be increased up to a 400-kHz bit rate (fast I
2
C mode) during the remaining data reads.
SPRU722C – November 2004 – Revised October 2006
Bootloader Features
43
