levels of priority: default priority and high priority. If the priority level bit is set, then that channel has
higher priority than all other channels at default priority. If multiple channels are set for high priority,
then the channel number is used to determine relative priority among all the high priority channels.
The priority bit for a channel can be set using the
DMA Channel Priority Set (DMAPRIOSET)
register and cleared with the
DMA Channel Priority Clear (DMAPRIOCLR)
register.
Note:
If one peripheral is mapped to two different channels, then the application should either use
the default mapping for that peripheral or change the default mapping to another source.
For example, if UART1 channels 8 and 9 are enabled for use, then even if channels 22 and
23 are disabled, they must be mapped to software or another peripheral (if available).
9.2.3
Arbitration Size
When a μDMA channel requests a transfer, the μDMA controller arbitrates among all the channels
making a request and services the μDMA channel with the highest priority. Once a transfer begins,
it continues for a selectable number of transfers before rearbitrating among the requesting channels
again. The arbitration size can be configured for each channel, ranging from 1 to 1024 item transfers.
After the μDMA controller transfers the number of items specified by the arbitration size, it then
checks among all the channels making a request and services the channel with the highest priority.
If a lower priority μDMA channel uses a large arbitration size, the latency for higher priority channels
is increased because the μDMA controller completes the lower priority burst before checking for
higher priority requests. Therefore, lower priority channels should not use a large arbitration size
for best response on high priority channels.
The arbitration size can also be thought of as a burst size. It is the maximum number of items that
are transferred at any one time in a burst. Here, the term arbitration refers to determination of μDMA
channel priority, not arbitration for the bus. When the μDMA controller arbitrates for the bus, the
processor always takes priority. Furthermore, the μDMA controller is held off whenever the processor
must perform a bus transaction on the same bus, even in the middle of a burst transfer.
9.2.4
Request Types
The μDMA controller responds to two types of requests from a peripheral: single or burst. Each
peripheral may support either or both types of requests. A single request means that the peripheral
is ready to transfer one item, while a burst request means that the peripheral is ready to transfer
multiple items.
The μDMA controller responds differently depending on whether the peripheral is making a single
request or a burst request. If both are asserted, and the μDMA channel has been set up for a burst
transfer, then the burst request takes precedence. See Table 9-2 on page 682, which shows how
each peripheral supports the two request types.
Table 9-2. Request Type Support
Event that generates Burst Request
Event that generates Single Request
Peripheral
FIFO half full
FIFO not empty
ADC
WFIFO Level (configurable)
None
EPI WFIFO
NBRFIFO Level (configurable)
None
EPI NBRFIFO
Trigger event
None
General-Purpose Timer
Trigger event
None
GPIO
TX FIFO Level (configurable)
TX Buffer Not Full
I
2
C TX
RX FIFO Level (configurable)
RX Buffer Not Empty
I
2
C RX
TX FIFO Level (fixed at 4)
TX FIFO Not Full
SSI TX
June 18, 2014
682
Texas Instruments-Production Data
Micro Direct Memory Access (μDMA)
