Texas Instruments TLV2553EVM, Manual

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+5 V
+5 V
REF+
REF-
OUTF
GNDF
OUTS
GNDS
IN
EN
REF3240
1 k
1
P
F
-
+
+
OPA320
0.5
10
P
F
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EVM Analog Interface
5 SBAU247A – June 2015 – Revised September 2019
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TLV2553EVM-PDK Evaluation Module
2.2 Onboard ADC Reference
The EVM does not include a provision for driving the reference input of the TLV2553 from an external
source. The reference input signal path is entirely self-contained on the TLV2553EVM and consists of the
REF3240, a 4.096-V precision voltage reference whose output is heavily low-pass filtered and buffered by
the OPA320, a precision op amp that has low output impedance over a sufficiently wide frequency range.
The schematic is shown in
Figure 2 .
Figure 2. Onboard Reference Signal Path
The 10-µF ceramic capacitor at the output of the OPA320 provides additional load decoupling and
effectively lowers the output impedance of the reference drive circuit at high frequencies.
3 Digital Interfaces
As noted in Section 1 , the EVM interfaces with the PHI that, in turn, communicates with the computer over
USB. There are two devices on the EVM with which the PHI communicates: the ADC (over SPI) and the
EEPROM (over I
2
C). The EEPROM comes pre-programmed with the information required to configure and
initialize the TLV2553EVM-PDK platform. When the hardware is initialized, the EEPROM is no longer
used.
3.1 SPI for ADC Digital IO
The TLV2553EVM-PDK supports all three ADC interface modes (8-, 12-, and 16-bit modes), as detailed in
the
TLV2553 data sheet. MSB- or LSB-first options are also supported. An important note concerning the
TLV2553 that is not clarified in the TLV2553 datasheet is that in 16-bit, LSB-first mode the four MSBs of
the DATA OUT word are zeroes (compare this with Figure 37 of the TLV2553 datasheet).
The EVM uses a 5-V supply for powering the TLV2553, and therefore the ADC digital I/O interface
operates on 5-V logic levels. However, the PHI requires 3.3-V logic levels for proper operation, and for this
reason the EVM includes the TXB0106 (U8), a 5-V to 3.3-V bidirectional level translator.
The digital I/O lines also include 50- Ω series resistors to minimize ringing and delay mismatches between
the SPI interface signals.