Texas Instruments TLV2553EVM, Manual

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+5 V
Input
Signal
Source
AINx
-
+ +
OPA4322
50
1 nF
1 M
EVM Analog Interface
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4 SBAU247A – June 2015 – Revised September 2019
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Copyright © 2015–2019, Texas Instruments Incorporated
TLV2553EVM-PDK Evaluation Module
2 EVM Analog Interface
At a system level, the analog portion of the TLV2553 consists of the 11 analog input channels and the dc
reference voltage input. As with most SAR ADCs, the analog inputs of the TLV2553 are not high-
impedance ports. These inputs terminate in switched-capacitor networks that draw load current when the
switches are closed. The dynamic nature of the load currents produces dynamic errors in the
corresponding input voltage signals and ADC accuracy can degrade if these errors are not managed
carefully. Low source impedance is critical to minimizing these errors; minimizing source impedance
requires careful design of the ADC input signal paths.
2.1 ADC Analog Input Signal Path
The 11 analog input signal paths are designed so that the ADC provides accurate results even with signal
sources that have relatively high output impedance. The schematic (for one channel) is shown in
Figure 1 .
Figure 1. Input Signal Path Schematic (Single Channel)
The OPA4322 unity-gain buffers individually decouple the input signal source on each channel from the
ADC input load current. The buffer inputs are pulled down to GND by the 1-M
Ω
resistors to ensure safe
and predictable operating conditions on the board even when the inputs are left floating. Of course, the
tradeoff with this approach is that the EVM analog input impedance is lower (only 1 M
Ω
) but the inputs
can still support a wide range of source impedances without introducing significant gain error.
The buffered ADC inputs are accessible through the even-numbered pins of J2 (that is, J2.Pin2 through
J2.Pin22). The odd-numbered pins of J2 (J2.Pin1 through J2.Pin27) are shorted together on the board
and must be jumpered to any one of the even-numbered pins marked
GND (J2.Pin28), PFS (J2.Pin26), or
NFS (J2.Pin24), depending on whether the ADC inputs must be driven from an external source (such as a
function generator, sensor, and so forth) or by one of the onboard sources.
Note that J2.Pin24 and J2.Pin26 are the outputs of the onboard dc voltage sources and have nominal
values of approximately 100 mV and 4 V, respectively. These pins are useful for debugging any gross
problems with the op-amp buffers or the ADC. However, for default operation (that is, inputs are from
external sources), the odd-numbered pins of J2 must be connected to J2.Pin28 (GND). The jumper
settings for J2 are summarized in
Table 1 .
Table 1. JP1 - JP2: Analog Interface Connections
ADC
Input Value J2.Pin24 ↔ J2.Pin23 J2.Pin26 ↔ J2.Pin25 J2.Pin28 ↔ J2.Pin27
External Any Open Open Closed
PFS 4 V Open Closed Open
NFS 100 mV Closed Open Open
NOTE: In addition to configuring J2 according to Table 1 , install shunts at the locations
corresponding to the appropriate input channels as well.