Texas Instruments TLV1562 Application Report Download Page 43

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Software Overview

Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP

Start

Initialize DSP

Wait States, AR Pointer, IRQ Table, Data Memory, Serial Port

Initialize SPI

Active Transmitter, Use Frame Sync,

Generate External Clock

SAVE_INTO_MEMORY = 1

SAVE_INTO_MEMORY = 0

Initialize DSP Memory For Sample Store
AR7 Points to The First Store Location
AR0 Points to The Table End
ADCOUNT = Table Size (Number of Samples)

Initialize (Id) The Two ADC Registers
CR0 = CR0_SEND
CR1 = CR1_SEND

IME CALABRATION = 1

Calibrate Internal Midscale Error

IME CALABRATION = 0

SME CALABRATION = 1

Calibrate System Midscale Error

SME CALABRATION = 0

Start Sampling

This Has Been Initialized

by The WR 1/0 Transmit

Wait 450 ns

Table End Reached?

(AR7 = AR0 ?)

Read Sample Into DSP

AD_SAMPLE = Port (ADC)

SEND_OUT_PARALLEL = 1

SEND_OUT_PARALLEL = 0

Copy Last Sample to Parallel DAC

SEND_OUT_SERIAL = 1

SEND_OUT_SERIAL = 0

Copy Last Sample to Serial DAC

if Send Register is Empty

SAVE_INTO_MEMORY = 0

SAVE_INTO_MEMORY = 1

Store Sample Into Memory

Save Sample to AR7 – Pointed Location

Yes

Reset Actual Memory Pointer

AR7= First Memory Store

Location = Data_Loc_A

Increase I/O-Wait States to 7

Wait 5(6) ADC Clock Cycles

Started at Time Stamp

tC(RD) = 800 ns (With 8 MHz ADC Clock)

Figure 10. Flow Chart Mono Continuous Mode

Summary of Contents for TLV1562

Page 1: ...Interfacing the TLV1562 Parallel ADĆConverter to the TMS320C54x DSP July 1999 Advanced Analog Products SLAA040 Application Report ...

Page 2: ...CONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to ...

Page 3: ...ing RD 12 7 3 Mono Interrupt Driven Mode Using CSTART 14 7 4 Dual Interrupt Driven Mode 15 7 5 Mono Continuous Mode 16 7 6 Dual Continuous Mode 17 8 Software Overview 18 8 1 Software Development tools 18 8 2 DSP Memory Map 18 8 3 Programming Strategies for the C54x Explanations 20 8 3 1 Optimizing CPU Resources for Maximum Data Rates 20 8 3 2 Address and Data Bus for I O Tasks 20 8 3 3 Timer Outpu...

Page 4: ...ftware for all Modes except C Callable 41 8 6 2 Mono Mode Interrupt Driven Software Using RD to Start Conversion 46 8 6 3 Calibration of the ADC 53 8 6 4 Mono Mode Interrupt Driven Software Using CSTART to Start Conversion 58 8 6 5 Dual Interrupt Driven Mode 66 8 6 6 Mono Continuous Mode 74 8 6 7 Dual Continuous Mode 80 8 6 8 C Callable 86 9 Summary 93 10 References 93 ...

Page 5: ...rnal Clock 33 9 Flow Chart Dual Interrupt Driven Mode Using CSTART to Start Conversion 35 10 Flow Chart Mono Continuous Mode 37 11 Flow Chart Dual Continuous Mode 39 List of Tables 1 Signal Connections 7 2 3 Position Jumpers 8 3 2 Position Jumpers 8 4 DSP DAC Interconnection 9 5 DSP Serial Port Signals and Registers 10 6 DSP Algorithm for Writing to the ADC 12 7 DSP Algorithm for Mono Interrupt Dr...

Page 6: ...vi SLAA040 ...

Page 7: ...tween the TLV1562 10 bit parallel output analog to digital converter ADC and the TMS320C54x digital signal processor DSP The report describes the hardware and software needed to interface the C54x DSP to the TLV1562 ADC which is intended for applications such as industrial control and signal intelligence in which large amounts of data must be processed quickly The first sections describe the basic...

Page 8: ...rter integrates the CSTART signal to coordinate sampling and conversion timing without using the parallel bus Since the TMS320C542 DSP has no second general purpose output this signal is generated with the signal CSTART from the address decoder 2 3 1 Suggestions for the C54x to TLV1562 Interface The following paragraphs describe two suggested interfaces between the C54x and the TLV1562 2 3 1 1 The...

Page 9: ...ated through A0 A1 and simplifies the software code CAUTION ThetimetEN DATAOUT betweentheRD high to low transition generated by the DSP and the arrival of valid ADC output data on the data bus is related to the capacitive load of the bus In most cases the ADC come out of the 3 state mode and supplies the correct voltage levels onto the bus lines in less than 50 ns Thus the minimum number of I O wa...

Page 10: ...result since the ADC will signal that the conversion has finished during the logic low transition of the INT signal The following timing diagram shows the interface behavior of the ADC whether the timing is correct or not The following figure shows what happens when the RD falling edge is timed wrong Although RD falls nearly 1 2 of one cycle too late the conversion result is valid on the 5th clock...

Page 11: ...mmsDAC This 10 bit data converter has a parallel interface and is able to update its output with 100 MSPS The two outputs on the 28 pin package can each drive a current between 2 mA and 20 mA with an output resistance 100 kΩ ideal current source output impedance The data bus and the address decoder provide the interface to the DSP Parallel DAC THS5651 CLK D 0 9 DSP TMS320C542 CLKOUT A 0 1 11b D 0 ...

Page 12: ...oupled Level shifting could be done with single supply op amps The absolute voltage values applied to VREFP VREFM and the analog input should not be greater than the AVDD supply minus 1 V or lower than 0 8 V Other input restrictions apply so consult the TLV1562 data sheet for further information The digital output is full scale when the analog input is equal to or greater than the voltage on VREFP...

Page 13: ...ine A0 JP5 34 J11 2 addr decoder for CS and CSTART A1 JP5 35 J11 1 addr decoder for CS and CSTART D0 JP3 35 J10 13 D0 D1 JP3 34 J10 15 D1 D2 JP3 8 J10 17 D2 D3 JP3 12 J10 19 D3 D4 JP3 11 J10 21 D4 D5 JP3 15 J10 23 D5 D6 JP3 14 J10 25 D6 D7 JP3 18 J10 27 D7 D8 JP3 17 J10 29 D8 D9 JP3 21 J10 31 D9 Serial Interface to the DAC TLC5618A BCLKR JP1 14 J11 25 SCLK BCLKX JP1 17 J11 23 SCLK BFSR JP1 20 J11 ...

Page 14: ... W13 Connects REFLO TLV5651 to Vcc or GND Disable internal reference Enable internal reference W14 Connects SCLK TLC5618AA to BCLKX or J8 BNC Normal DSP mode An external clock source drives the SCLK pin instead of the DSP W15 Connects CLK TLV5651 to CLKOUT DSP or J7 BNC Normal DSP mode An external clock source drives the CLK pin instead of the DSP W23 Connects CSTART to A0 A1 or XF A0 and A1 used ...

Page 15: ...BDX BDR DATA IN The following statements describe the generation and application of the configuration and control signals The DSP BCLKX output provides a 20 MHz data clock which is a divide by 2 of the DSP master clock The DSP BDX output supplies the 16 bit control and data move to the TLC5618A at DATA IN The DSP BFSX frame synchronization signal connected to CS triggers the start of a new frame o...

Page 16: ... the next 16 clock cycles from the BCLKX terminal The BFSX signal is applied to the TLC5618A CS terminal BFSR Frame sync receive This signal frames the receive data The DSP begins to receive data on the falling edge of BFSR and continues to recognize valid data for the following 16 clocks from BCLKR This signal is not important for this application Table 5 lists the serial port pins and registers ...

Page 17: ...FSX initiates the transfer at the beginning of the packet and BCLKX clocks the bit transfer The corresponding pins on the receive device are BDR BFSR and BCLKR respectively The transmit is executed by the autobuffer mode This means there is no need to write to the serial port output buffer Instead the DSP continuously sends the data located in the memory beginning on AXR When all data are sent def...

Page 18: ...rsion and serial transmission steps only once Although this mode produces continuous sampling data the use of other modes is recommended One reason is the CS signal has to stay low during the whole sampling conversion time An interesting advantage of this mode is its ability to control the start sample time The RD signal controls the sampling and converting Every falling edge of RD stops the sampl...

Page 19: ...riven mode in CR0 2 3 1 set CS deselect ADC optional with APD 0 2 clear CS Select ADC Note if Hardware Auto power down is enabled Chip select has to be used otherwise CS can be left high 3 Wait for tD CSL sample 1ADCSYSCLK tD CSL sample 5ns APD 0 tD CSL sample 500ns APD 1 6 5 26 25 4 Clear RD ADC goes over from sampling into conversion 5 Wait until INT goes low alternative ignore the INT signal wa...

Page 20: ...DSPCLK STEPS TIMING NOTES APD 0 ADCSYCLK 7 5 MHz APD 0 ADCSYCLK 10 MHz APD 1 ADCSYCLK 10 MHz APD 1 ADCSYCLK 10 MHz 1 Set CS Deselect ADC 2 Clear CSTART tTis starts sampling 3 Wait for tW CSTARTL tW CSTARTL 100 ns APD 0 tW CSTARTL 600 ns APD 1 4 4 24 24 4 Set CSTART This starts the conversion 5 Wait until INT goes low Alternative ignore the INT signal wait 14ns 5 ADCSYSCLK and goto step number 7 33...

Page 21: ...LK 10MHz APD 1 ADCSYCLK 10MHz 1 Set CS Deselect ADC 2 Clear CSTART This starts sampling 3 Wait for tW CSTARTL tW CSTARTL 100ns APD 0 tW CSTARTL 600ns APD 1 4 4 24 24 4 Set CSTART This starts the conversion 5 Wait until INT goes low Alternative ignore the INT signal wait 210ns 10 ADCSYSCLK and go to step number 7 62 48 62 48 6 Wait the time tD INTL CSL tD INTL CSI 10 ns 1 1 1 1 7 Clear CS Select th...

Page 22: ... TIMING NOTES APD 0 ADCSYCLK 7 5 MHz APD 0 ADCSYCLK 10 MHz APD 1 ADCSYCLK 10 MHz APD 1 ADCSYCLK 10 MHz 0 Initialization N A N A Write all configuration data to the ADC Activate the mono continuous mode in CR0 2 3 N A N A 1 Set CS Deselect ADC N A N A 2 wait for t SAMPLE1 t SAMPLE1 100 ns 4 4 N A N A 3 Clear CS Select ADC N A N A 4 Clear RD Start conversion N A N A 5 Wait the time tEN DATAOUT tEN D...

Page 23: ...nuous mode in CR0 2 3 N A N A 1 Set CS deselect ADC N A N A 2 Wait for t SAMPLE1 t SAMPLE1 100 ns 4 4 N A N A 3 Clear CS Select ADC N A N A 4 Clear RD Start conversion 5 Wait the time tEN DATAOUT tEN DATAOUT 41 ns 2 2 N A N A 6 Read first sample out from the data port reset RD signal Caution the first result after initialization is trash N A N A 7 Wait for the time t CONV1 minus step 7 and 8 to en...

Page 24: ...ader This prevents software bugs from appearing through a forgotten correction of a related instruction BSPC_BUFFER_START set 00800h memory location 800h for the start address of the SPC buffer AXR BSPC_BUFFER_START assign the starting address of auto buffer 8 1 Software Development tools The DSKplus Starter Kit of the TMS320C54x comes with a free compiler to generate an absolute object file from ...

Page 25: ...00FFh 0100h 017Fh 0180h 07FFh 0800h 0FFFh 1000h 1009h 100Ah 17FFh 1800h 27FFh 2800h EFFFh F000h F7FFh F800h FF7Fh FF80h FFFFh 01FFh 0200h 027Fh 0280h 02FFh 0300h Reserved Memory by The DSKplus Board Memory Mapped Register Scratch Pad RAM DRAM See Program Memory Software Data Memory All Variables Tables to Store Data Samples External Table 1 0000h 005Fh 0060h 007Fh 0080h 27FFh 1800h 1FFFh 2000h 27F...

Page 26: ...send a digital result to one of the DACs Unfortunately this task is impossible at the ADC s maximum throughput of 40 MIPS Therefore this software only stores the samples and optionally moves them out to the DACs Enabling all options at the same time prevents the application from running at maximum throughput The following switches enable disable these actions SAVE_INTO_MEMORY set 00001h set 1 to s...

Page 27: ...tivate CSTART 8 3 6 Interfacing the Serial DAC 5618A to the DSP A buffered serial port on the C542 board interfaces the TLC5618A DAC The advantage of using a buffered serial port compared to the standard port is the auto buffer mode This allows the programmer to save CPU power A background process takes the data from a defined memory location table and moves it out to the serial port An interrupt ...

Page 28: ...oto instruction Since the C54x has a pipeline to allow execution of one instruction in one clock cycle a simple branch instruction will take four cycles for execution Example GOTO MARK MARK DP 1 ARP 5 The program counter PC points after the last instruction ARP 5 past 6 sysclk cycles However this can be optimized using a delayed branch DGOTO MARK DP 1 ARP 5 MARK The time to execute the same number...

Page 29: ...onversation mode This application report provides one file for each mode Many settings 2s complement channels etc must be selected This software allows a variation of those parameters in the program header A simple switch enables or disables each component After recompiling the code with a special setting of all switches the code becomes much smaller and easier to understand The if elsif endif ins...

Page 30: ...ight result in slightly different results for a steady stable input function related to the sampling time variations The only way to prevent this is to control the conversion with the on chip timer of the DSP Unfortunately the maximum throughput falls off with increased requirements for CPU power 8 4 1 2 Timed Solution How long the ADC requires for conversion must be factored into the software flo...

Page 31: ...need to control any data acquisition software flow Easy software debugging and implementing of new features not critical for any software changes The software compensates for variations in timing given in data sheets for conversion and the real time until the flag goes high Disadvantages Program overhead uses a lot of resources which is critical for maximum throughput performance Watchdog algorith...

Page 32: ...independent from each other however performing more than one calibration does not make sense see data sheet Features not listed in Table 12 must be changed directly in the two data words CR0 1 that are sent to the ADC In general correct bit setting is described in the data sheet However the file CONSTANT ASM includes a look up table to simplify the task of setting the right bits in CR0 and CR1 Thu...

Page 33: ...XTERNAL in step 2 because the clock source is defined in the program header and therefore will be justified behind the step 2 instructions later in the program That is why in step 2 only the CH1 value is replaced with PAIR_B but nothing else has been specified 8 4 1 6 Common Software for all Modes The files CONSTANT ASM and VECTORS ASM include constant definitions and the interrupt vector table Th...

Page 34: ...quirements to interface the C54x to the ADC are provided in Tables 6 and 7 The STEP numbers given there can be found again as Marker in the code This helps to debug and verify the code Code verification To verify the software the user must change the code in the MONIDM1 ASM file and save those changes The next step is to recompile the three ASM files by executing the AUTO BAT batch file If compile...

Page 35: ...of Conversion Poll INTO Pin Until h 0 Transition Occurs INTO_DRINEN 1 Main Program Stay in Idle Mode NO_INTO_SIGNAL 1 Wait Until End of Conversion Wait For a Certain Time 1 INTO 2 Read Sample SEND_OUT_PARALLEL 1 SEND_OUT_PARALLEL 1 Copy Last Sample to Parallel DAC SEND_OUT_SERIAL 1 SEND_OUT_SERIAL 0 Copy Last Sample to Serial DAC if Send Register is Empty Start New Conversion SAVE_INTO_MEMORY 0 SA...

Page 36: ...ps to debug and verify the code IMPORTANT NOTE The code has been optimized during the software development to maximize the data throughput It was found that CSTART can be pulled down earlier than the data read instruction is performed by the DSP The advantage is to save the 100 ns wait time in STEP 6 because the data read requires at least 100 ns Therefore CSTART gets pulled back high directly aft...

Page 37: ...System Midscale Error IME CALABRATION 0 Start Sampling Pull Down CSTART Wait 100 ns Stop Sampling and Start Conversion Reset CSTART Set Back High Table End Reached AR7 AR0 POLLING_DRIVEN 1 Wait Until End of Conversion Poll INTO Pin Until h 0 Transition Occurs INTO_DRINEN 1 Main Program Stay in Idle Mode NO_INTO_SIGNAL 1 Wait Until End of Conversion Wait For a Certain Time 1 INTO 2 SEND_OUT_PARALLE...

Page 38: ...the more precisely the sampling capacitor will be charged assuming that the noise located by RD is negligible In this algorithm CSTART can be taken high right after the data has been read by the DSP without any wait instruction Therefore the maximum throughput is gained because the 100 ns sampling time is saved Test results showed a maximum throughput of more than 1 2 MSPS approximately 20 of gain...

Page 39: ...LIRQ1 ASM Includes the complete software algorithm to control the Dual IRQ Driven Mode CALIBRAT ASM Calibration procedure of the DAC CONSTANT ASM Common file of all modes constants definition VECTORS ASM Common file of all modes IRQ vector table Other Files linker cmd Organization of the DSP memory data and program memory auto bat Batch file to start the compiler for the dual interrupt driven soft...

Page 40: ...hput This variation will be found in the code The data acquisition is done in a small number of steps that explains everything inside the code Code verification To verify the software the user must change the code in the DUALIRQ1 ASM file and save those changes The next step is to recompile the four ASM files by executing the AUTO BAT batch file If compiler and linker finish without error messages...

Page 41: ...dscale Error IME CALABRATION 0 Start Sampling Pull Down CSTART Wait 100 ns Stop Sampling and Start Conversion Reset CSTART Set Back High Table End Reached AR7 AR0 POLLING_DRIVEN 1 Wait Until End of Conversion Poll INTO Pin Until h 0 Transition Occurs INTO_DRINEN 1 Main Program Stay in Idle Mode NO_INTO_SIGNAL 1 Wait Until End of Conversion Wait For a Certain Time 1 INTO 2 SEND_OUT_PARALLEL 1 SEND_...

Page 42: ...ile to start the compiler for the mono continuous software asm500 exe C54x Code compiler lnk500 exe C54x linker The timing requirements to interface the C54x to the ADC are provided in Table 11 The STEP numbers given there can be found again as Marker in the code This helps to debug and verify the code Code verification To verify the software the user must change the code in the MONOCON1 ASM file ...

Page 43: ...IME CALABRATION 0 SME CALABRATION 1 Calibrate System Midscale Error SME CALABRATION 0 Start Sampling This Has Been Initialized by The WR 1 0 Transmit Wait 450 ns Table End Reached AR7 AR0 Read Sample Into DSP AD_SAMPLE Port ADC 1 SEND_OUT_PARALLEL 1 SEND_OUT_PARALLEL 0 Copy Last Sample to Parallel DAC SEND_OUT_SERIAL 1 SEND_OUT_SERIAL 0 Copy Last Sample to Serial DAC if Send Register is Empty SAVE...

Page 44: ...e to start the compiler for the dual continuous software asm500 exe C54x Code compiler lnk500 exe C54x linker The timing requirements to interface the C54x to the ADC are provided in Table 12 The STEP numbers given there can be found again as Marker in the code This helps to debug and verify the code Code verification To verify the software the user must change the code in the DUALCON1 ASM file an...

Page 45: ... System Midscale Error SME CALABRATION 0 Start Sampling This Has Been Initialized by The WR 1 0 Transmit Wait 450 ns Table End Reached AR7 AR0 Read Sample A A Port ADC 1 SEND_OUT_PARALLEL 1 SEND_OUT_PARALLEL 0 Copy Last Sample to Parallel DAC SEND_OUT_SERIAL 1 SEND_OUT_SERIAL 0 Copy Last Sample to Serial DAC if Send Register is Empty SAVE_INTO_MEMORY 0 SAVE_INTO_MEMORY 1 Store Sample Into Memory S...

Page 46: ...sembler mnem2alg exe Mnemonic algebraic instruction converter asm500 exe C54x Code compiler lnk500 exe C54x linker rts lib Library to organize boot loader The timing requirements for interfacing the C54x to the ADC are provided in Table 13 The STEP numbers given there can be found again as Marker in the code This helps to debug and verify the code Code verification The user only needs to edit the ...

Page 47: ... TLV1562 INDEX MODE 0 CH1 set 00000h Channel selection is Channel 1 CH2 set 00001h Channel selection is Channel 2 CH3 set 00002h Channel selection is Channel 3 CH4 set 00003h Channel selection is Channel 4 PAIR_A set 00000h Channel selection is Pair A PAIR_B set 00003h Channel selection is Pair B MONO_INT set 00000h Conversion mode selection is Mono Interrupt DUAL_INT set 00004h Conversion mode se...

Page 48: ... clock source calibrated inputs into Mono Continuous Mode send CH4 MONO_CONTINUOUS SINGLE_END CLK_EXTERNAL CALIB_OP port xxxxh send send the value over the Data lines to the TLCV1562 memory organization table write of samples for the C54x num_data_A set 00200h Number of data from channel A num_data_B set 00200h Number of data from channel B num_data_C set 00200h Number of data from channel C num_d...

Page 49: ...TED 1998 C BY TEXAS INSTRUMENTS INCORPORATED REFERENCE TMS320C54x DSKPlus User s Guide TI 1997 title Vector Table mmregs width 80 length 55 reset goto _MAIN 00 RESET DO NOT MODIFY IF USING DEBUGGER nop nop nmi goto START 04 non maskable external interrupt nop nop trap2 goto trap2 08 trap2 DO NOT MODIFY IF USING DEBUGGER nop nop space 52 16 0C 3F vectors for software interrupts 18 30 int0 return_fa...

Page 50: ...terrupt nop nop nop bxint goto BXINT0 54 BSP transmit interrupt nop nop trint goto trint 58 TDM receive interrupt nop nop txint return_enable 5C TDM transmit interrupt nop nop nop int3 return_enable 60 external interrupt int3 nop nop nop hpiint goto hpiint 64 HPIint DO NOT MODIFY IF USING DEBUGGER nop nop space 24 16 68 7F reserved area ...

Page 51: ...area for the TLV1562 interface Program stack 0x0080 M monocon1 MAP O monocon1 OUT e START monocon1 obj MEMORY PAGE 0 VECT origin 0200h length 0080h PROG origin 0300h length 0400h PAGE 1 RAMB0 origin 1800h length 1600h SECTIONS text PROG PAGE 0 vectors VECT PAGE 0 data RAMB0 PAGE 1 variabl RAMB0 PAGE 1 8 6 1 4 Auto bat The batch file to compile changes is specified for each mode but in general look...

Page 52: ...RUMENTS INCORPORATED REFERENCE TMS320C54x User s Guide TI 1997 TMS320C54x DSKPlus User s Guide TI 1997 Data Aquisation Circuits TI 1998 title MONOIDM1 mmregs width 80 length 55 version 542 the next 4 lines setsect have to be enabled if the DSKplus code generator instead of the asm500 exe tools are in use setsect vectors 0x00180 0 sections of code setsect text 0x00200 0 these assembler directives s...

Page 53: ...ersion is done INT0_DRIVEN set 00000h software uses Interrupt INT0 to organize conversion NO_INT0_SIG set 00000h INT0 signal not in use interface is controlled with timing solution SAVE_INTO_MEMORY set 00001h store the samples into DSP memory defined in constants asm SEND_OUT_SERIAL set 00000h send the samples always to the serial DAC SEND_OUT_PARALLEL set 00001h update always the parallel DAC wit...

Page 54: ...eat num_data_A 1 data data_loc_A TEMP fill memory table 1 repeat num_data_B 1 data data_loc_B TEMP fill memory table 2 repeat num_data_C 1 data data_loc_C TEMP fill memory table 3 repeat num_data_D 1 data data_loc_D TEMP fill memory table 4 if SEND_OUT_SERIAL SERIAL_DAC_INI initialize the serial interface to send out the samples for the serial DAC set up the serial interface for a DSP DAC 5618A co...

Page 55: ... AR5 points to the IFR register only for polling mode endif DP AD_DP ZERO 00000 set the dummy send value initialize the send values to set up the two programmable register of the ADC CR0_SEND CH1 MONO_INT SINGLE_END CLK_INTERNAL NO_CALIB_OP CR1_SEND NO_SW_PWDN NO_AUTO_PWDN NO_2COMPLEMENT NO_DEBUG RES_10_BIT RD_CONV_START change some of the possible modes by variation of the bit setting in the file...

Page 56: ...alue to the ADC port DEACTIVE ZERO deselect ADC CShigh NOP wait for tW CSH 50ns ADC_mono_IRQ_Start read samples and store them into memory ADC_mono_IRQ_Start STEP2 TEMP port ADC select ADC CS low change address bus signal STEP3 repeat 4 NOP wait for tD CSL SAMPLE 1SYSCLK 6 STEP4 XF 0 clear RD STEP5 if POLLING_DRV wait until INT goes low in polling the INT0 pin M1 TC bit AR5 15 0 test is the INT0 B...

Page 57: ...activate ADC CS again endif if AUTO_PWDN deselect select the ADC with CS requirment in Auto power down mode TEMP port DEACTIVE deselect ADC TEMP port ADC activate ADC CS again repeat 18 nop wait for 20 clock cycles t APDR 500ns endif XF 0 clear RD step 4 call STORE handle storing of the samples into memory and serail DAC if INT0_DRIVEN return return from routine back to IRQ_INT0 else goto STEP5 go...

Page 58: ...de of the DAC data BDXR ADSAMPLE send out the sample to the serial DAC SEND_SERIAL_END endif if SAVE_INTO_MEMORY test for table end set pointer back if true TC AR0 AR7 is AR0 AR7 table end reached if NTC goto STORE_END set pointer back to table start AR7 data_loc_A point to first date location of the storage table endif STORE_END RETURN jump back into data aquisition routine IRQ_INT0 Interrupt rou...

Page 59: ...nged anywhere during the program sect text if IME_CALIBRATION CALIBRAT_INTERNAL_MID_SCALE performs an internal calibration of the ADC to offset for internal device errors basic idea do a error calibration in mono interrupt driven mode using CSTART for conversion but use the channel single differential input information already set up in the CR0_send register from CALIBRAT_INTERNAL_MID_SCALE DP AD_...

Page 60: ...on mode verify ADC register CR0 CR1 write CR1 to reset old CSTART mode initialization because otherwise the ADC never sets back its INT pin to show a sample is available CR_PROBLEM SW_PWDN NO_AUTO_PWDN NO_2COMPLEMENT NO_DEBUG RES_10_BIT RD_CONV_START port ADC CR_PROBLEM Address decoder sets CS low WR low and send CR_PROBLEM value to the ADC NOP wait for tW CSH 50ns write CR1 initialize the send va...

Page 61: ... ZERO deselect ADC CS high NOP wait for tW CSH 50ns write CR0 port ADC CR0_SEND send CR0 value to the ADC port DEACTIVE ZERO deselect ADC CS high NOP wait for tW CSH 50ns return return from call endif if SME_CALIBRATION CALIBRAT_SYSTEM_MID_SCALE performs an internal calibration of the ADC to offset for the device midscale error and input offset basic idea do a error calibration in mono interrupt d...

Page 62: ...her use set mode for intermal offset calibration CR_CALIBRA SYS_OFF_CALIB set internal calibration mode verify ADC register CR0 CR1 write CR1 to reset old CSTART mode initialization because otherwise the ADC never sets back its INT pin to show a sample is available CR_PROBLEM SW_PWDN NO_AUTO_PWDN NO_2COMPLEMENT NO_DEBUG RES_10_BIT RD_CONV_START port ADC CR_PROBLEM Address decoder sets CS low WR lo...

Page 63: ...se otherwise the ADC never sets back its int pin to show a sample is available CR_PROBLEM SW_PWDN NO_AUTO_PWDN NO_2COMPLEMENT NO_DEBUG RES_10_BIT RD_CONV_START port ADC CR_PROBLEM Address decoder sets CS low WR low and send CR_PROBLEM value to the ADC NOP wait for tW CSH 50nS write CR1 port ADC CR1_SEND Address decoder sets CS low WR low and send CR1 value to the ADC port DEACTIVE ZERO deselect AD...

Page 64: ...P Application Group ICKE Dallas CREATED 1998 C BY TEXAS INSTRUMENTS INCORPORATED REFERENCE TMS320C54x User s Guide TI 1997 TMS320C54x DSKPlus User s Guide TI 1997 Data Aquisation Circuits TI 1998 title MONOCST1 mmregs width 80 length 55 version 542 the next 4 lines setsect have to be enabled if the DSKplus code generator instead of the asm500 exe tools are in use setsect vectors 0x00180 0 sections...

Page 65: ... and A2 set timing mode use od IRQ or timer POLLING_DRV set 00001h software polls the INT0 pin to wait until conversion is done INT0_DRIVEN set 00000h software uses Interrupt INT0 to organize conversion NO_INT0_SIG set 00000h INT0 signal not in use interface is controlled with timing solution SAVE_INTO_MEMORY set 00000h store the samples into DSP memory defined in constants asm SEND_OUT_SERIAL set...

Page 66: ...40h repeat 35 data 00C0h AR7 copy INT0 INT1 clear all memory locations of the sampling table table where the samples will be stored DP AD_DP TEMP 00000h repeat num_data_A 1 data data_loc_A TEMP fill memory table 1 repeat num_data_B 1 data data_loc_B TEMP fill memory table 2 repeat num_data_C 1 data data_loc_C TEMP fill memory table 3 repeat num_data_D 1 data data_loc_D TEMP fill memory table 4 if ...

Page 67: ...point to first date location of the storage table AR0 num_data_A data_loc_A AR0 points to table end DP AD_DP ADCOUNT num_data_A initialize ADCOUNT with the number of required samples if POLLING_DRV AR5 IFR AR5 points to the IFR register only for polling mode endif DP AD_DP ZERO 00000 set the dummy send value initialize the send values to set up the two programmable register of the ADC CR0_SEND CH1...

Page 68: ...TIAL set differential input mode endif if IME_CALIBRATION call CALIBRAT_INTERNAL_MID_SCALE endif if SME_CALIBRATION call CALIBRAT_SYSTEM_MID_SCALE endif ADC_INI set ADC register CR0 CR1 ADC_INI write CR1 to reset old CSTART mode initialization because otherwise the ADC never sets back its int pin to show a sample is available CR_PROBLEM SW_PWDN NO_AUTO_PWDN NO_2COMPLEMENT NO_DEBUG RES_10_BIT RD_CO...

Page 69: ...M1 wait until INT signal goes high IFR 1 reset any old interrupt on pin INT0 elseif INT0_DRIVEN user main program area this could execute additional code go into idle state until the INT0 wakes the processor up USER_MAIN IDLE 2 the user software could do something else here goto USER_MAIN elseif NO_INT0_SIG instead of using the INT signal the processor waits for 6ADCSYSCLK 49ns and reads then the ...

Page 70: ...al buffer location DP 00000h point to page zero TC bitf SPC 01000h test is the XRDY Bit in SPC 1 if TC goto SEND_SERIAL_END don t send something until XDR is empty this has been included because the serial DAC TLC5618A is not able to understand endless data stream the CS should not become high before end of sending the 16th bit DP AD_DP reset Data page pointer to variables A ADSAMPLE 2 leftshift o...

Page 71: ... into data aquisition routine IRQ_INT0 Interrupt routine of the external interrupt input pin INT0 IRQ_INT0 call STEP2 initialize the next conversion and store results return_enable return from IRQ wake up from the IDLE mode BXINT0 Interrupt routine of the serial transmit interrupt of the buffered SPI BXINT0 return_enable interrupt is not in use sect text copy calibrat asm end ...

Page 72: ...E Dallas CREATED 1998 C BY TEXAS INSTRUMENTS INCORPORATED REFERENCE TMS320C54x User s Guide TI 1997 Data Aquisation Circuits TI 1998 title DUALIRQ1 mmregs width 80 length 55 version 542 setsect vectors 0x00180 0 sections of code setsect text 0x00200 0 these assembler directives specify setsect data 0x01800 1 the absolute addresses of different setsect variabl 0x01800 1 sections of code sect vector...

Page 73: ...are polls the INT0 pin to wait until conversion is done INT0_DRIVEN set 00000h software uses Interrupt INT0 to wait for end of conversion NO_INT0_SIG set 00000h INT0 signal not in use timing solution SAVE_INTO_MEMORY set 00001h store the samples into DSP memory SEND_OUT_SERIAL set 00000h store the last sample allways into serial buffer memory SEND_OUT_PARALLEL set 00001h store the last sample allw...

Page 74: ...cations of the sampling table table where the samples will be stored DP AD_DP TEMP 00000h repeat num_data_A 1 data data_loc_A TEMP fill memory table 1 repeat num_data_B 1 data data_loc_B TEMP fill memory table 2 repeat num_data_C 1 data data_loc_C TEMP fill memory table 3 repeat num_data_D 1 data data_loc_D TEMP fill memory table 4 if SEND_OUT_SERIAL SERIAL_DAC_INI initialize the serial interface ...

Page 75: ...o table end DP AD_DP ADCOUNT num_data_A initialize ADCOUNT with the number of required samples if POLLING_DRV AR5 IFR AR5 points to the IFR register only for polling mode endif DP AD_DP ZERO 00000 set the dummy send value initialize the send values to set up the two programmable register of the ADC CR0_SEND CH1 MONO_INT SINGLE_END CLK_INTERNAL NO_CALIB_OP CR1_SEND NO_SW_PWDN NO_AUTO_PWDN NO_2COMPL...

Page 76: ... are shorted to the correct voltage and after calibration the analog signal is to apply before doing any further signal conversion the calibration implementation is more or less inserted as an example if IME_CALIBRATION call CALIBRAT_INTERNAL_MID_SCALE endif if SME_CALIBRATION call CALIBRAT_SYSTEM_MID_SCALE endif ADC_INI set ADC register CR0 CR1 ADC_INI write CR1 to reset old CSTART mode initializ...

Page 77: ... down mode repeat 38 nop wait for 40 clock cycles t APDR 1000ns endif ISTEP4 XF 1 set CSTART STEP5 if POLLING_DRV wait until INT goes low in polling the INT0 pin M1 TC bit AR5 15 0 test is the INT0 Bit in IFR 1 if NTC goto M1 wait until INT signal went high IFR 1 reset any old interrupt on pin INT0 elseif INT0_DRIVEN user main program area this could execute additional code go into idle state unti...

Page 78: ..._OUT_PARALLEL store sample into the parallel buffer location if chosen port DAC1 CH1_ADSAMPLE update DAC output with sample one endif if SAVE_INTO_MEMORY store new sample into DSP data memory AR7 data CH1_ADSAMPLE write last sample of channel 1 into memory table AR6 data CH2_ADSAMPLE write last sample of channel 2 into memory table endif if SEND_OUT_SERIAL store sample into the serial buffer locat...

Page 79: ...et pointer back to table start AR7 data_loc_A point to first date location of the storage table AR6 data_loc_B point to first date location of the storage table endif STORE_END RETURN jump back into data aquisition routine IRQ_INT0 Interrupt routine of the external interrupt input pin INT0 IRQ_INT0 call STEP2 initialize the next conversion and store results return_enable return from IRQ wake up fr...

Page 80: ...on 542 setsect vectors 0x00180 0 sections of code setsect text 0x00200 0 these assembler directives specify setsect data 0x01800 1 the absolute addresses of different setsect variabl 0x01800 1 sections of code sect vectors copy vectors asm sect data copy constant asm AD_DP usect variabl 0 ACT_CHANNEL usect variabl 1 jump address to init new channel ADWORD usect variabl 1 send bytes to the ADC ADCO...

Page 81: ...esolution INTERNAL_CLOCK set 00001h use the internal clock of the ADC EXTERNAL_CLOCK set 00000h use the external clock of the ADC DIFF_INPUT_MODE set 00000h use differential mode instead of single ended inputs IME_CALIBRATION set 00000h do an Internal Midscale Error Calibration SME_CALIBRATION set 00000h do a System Midscale Error Calibration sect text _MAIN START INITIALIZATION disable IRQ sign e...

Page 82: ... is used by this program because the GoDSP debugger needs to do its backgroud interrupts INTM 0 enable global IRQ initialize storage table for the ADC samples AR7 data_loc_A point to first date location of the storage table AR0 num_data_A data_loc_A AR0 points to table end DP AD_DP ADCOUNT num_data_A initialize ADCOUNT with the number of required samples DP AD_DP ZERO 00000 set the dummy send valu...

Page 83: ...d be executed when the inputs are shorted to the correct voltage and after calibration the analog signal is to apply before doing any further signal conversion the calibration implementation is more or less inserted as an example if IME_CALIBRATION call CALIBRAT_INTERNAL_MID_SCALE endif if SME_CALIBRATION call CALIBRAT_SYSTEM_MID_SCALE endif ADC_INI set ADC register CR0 CR1 ADC_INI write CR1 port ...

Page 84: ...if chosen port DAC1 ADSAMPLE update DAC output endif if SAVE_INTO_MEMORY store new sample into DSP data memory AR7 data ADSAMPLE write last sample into memory table endif if SEND_OUT_SERIAL store sample into the serial buffer location DP 00000h point to page zero TC bitf SPC 01000h test is the XRDY Bit in SPC 1 if TC goto SEND_SERIAL_END don t send something until XDR is empty this has been includ...

Page 85: ...nter back to table start AR7 data_loc_A point to first date location of the storage table endif STORE_END RETURN jump back into data aquisition routine IRQ_INT0 Interrupt routine of the external interrupt input pin INT0 IRQ_INT0 return_enable interrupt is not in use BXINT0 Interrupt routine of the serial transmit interrupt of the buffered SPI BXINT0 return_enable interrupt is not in use sect text ...

Page 86: ...on 542 setsect vectors 0x00180 0 sections of code setsect text 0x00200 0 these assembler directives specify setsect data 0x01800 1 the absolute addresses of different setsect variabl 0x01800 1 sections of code sect vectors copy vectors asm sect data copy constant asm AD_DP usect variabl 0 ACT_CHANNEL usect variabl 1 jump address to init new channel ADWORD usect variabl 1 send bytes to the ADC ADCO...

Page 87: ...T_RESOLUT set 00000h use fastest mode 4 Bit resolution INTERNAL_CLOCK set 00001h use the internal clock of the ADC EXTERNAL_CLOCK set 00000h use the external clock of the ADC DIFF_INPUT_MODE set 00000h use differential mode instead of single ended inputs IME_CALIBRATION set 00000h do an Internal Midscale Error Calibration SME_CALIBRATION set 00000h do a System Midscale Error Calibration sect text ...

Page 88: ...s is even required if no IRQ routine is used by this program because the GoDSP debugger needs to do its backgroud interrupts INTM 0 enable global IRQ initialize storage table for the ADC samples AR7 data_loc_A point to first date location of the storage table AR0 num_data_A data_loc_A AR0 points to table end DP AD_DP ADCOUNT num_data_A initialize ADCOUNT with the number of required samples DP AD_D...

Page 89: ...n practice the calibration procedure should be executed when the inputs are shorted to the correct voltage and after calibration the analog signal is to apply before doing any further signal conversion the calibration implementation is more or less inserted as an example if IME_CALIBRATION call CALIBRAT_INTERNAL_MID_SCALE endif if SME_CALIBRATION call CALIBRAT_SYSTEM_MID_SCALE endif ADC_INI set AD...

Page 90: ...saving the samples into memory STORE if SEND_OUT_PARALLEL store sample into the parallel buffer location if choosen port DAC1 CH1_ADSAMPLE update DAC output with sample one endif if SAVE_INTO_MEMORY store new sample into DSP data memory AR7 data CH1_ADSAMPLE write last sample of channel 1 into memory table AR6 data CH2_ADSAMPLE write last sample of channel 2 into memory table endif if SEND_OUT_SER...

Page 91: ...AR0 table end reached if NTC goto STORE_END set pointer back to table start AR7 data_loc_A point to first date location of the storage table AR6 data_loc_B point to first date location of the storage table endif STORE_END RETURN jump back into data aquisition routine IRQ_INT0 Interrupt routine of the external interrupt input pin INT0 IRQ_INT0 return_enable interrupt is not in use BXINT0 Interrupt ...

Page 92: ...es of channel 2 will be stored beginning on 2100h TLV1562 3 0x2200 0x0080 80h samples of channel 3 will be stored beginning on 2200h Assembler Routine to Control the Interface to the ADC ASM1562 asm TITLE TLV1562 ADC Interface routine FILE DUALIRQ1 ASM FUNCTION MAIN PROTOTYPE void MAIN CALLS N A PRECONDITION N A POSTCONDITION N A DESCRIPTION main routine to use the mono interrupt driven mode and t...

Page 93: ...ct variabl 1 the last value sent to register CR1 CR_PROBLEM usect variabl 1 problem with initialization of this mode when repeated reset ZERO usect variabl 1 the value zero to send TEMP usect variabl 1 temporary variable isr_save usect variabl 1 memory location to save AR7 during interrupts ADSAMPLE usect variabl 1 last read sample Address Decoder constants ADC set 00002h activate A0 when TLV1562 ...

Page 94: ...D NO_SW_PWDN NO_AUTO_PWDN NO_2COMPLEMENT NO_DEBUG RES_10_BIT CST_CONV_START ADC_INI set ADC register CR0 CR1 ADC_INI write CR1 to reset old CSTART mode initialization because otherwise the ADC never sets back its int pin to show a sample is available CR_PROBLEM SW_PWDN NO_AUTO_PWDN NO_2COMPLEMENT NO_DEBUG RES_10_BIT RD_CONV_START port ADC CR_PROBLEM Address decoder sets CS low WR low and send CR_P...

Page 95: ...XF 1 wait for TW CSTARTL and set CSTART STORE saving the samples into memory STORE store new sample into DSP data memory AR7 data ADSAMPLE write last sample into memory table test for table end set pointer back if true TC AR0 AR7 is AR0 AR7 table end reached if NTC goto STORE_END finish conversion CPL 1 do stack pointer addressing AR7 pop restore AR7 AR6 pop restore AR6 A 0 clear ACCU RETURN jump ...

Page 96: ...Freising CREATED 1998 C BY TEXAS INSTRUMENTS INCORPORATED REFERENCE TMS320C54x DSKPlus User s Guide TI 1997 title Vector Table mmregs width 80 length 55 ref _c_int00 reset goto _c_int00 00 RESET DO NOT MODIFY IF USING DEBUGGER nop nop nmi goto START 04 non maskable external interrupt nop nop trap2 goto trap2 08 trap2 DO NOT MODIFY IF USING DEBUGGER nop nop space 52 16 0C 3F vectors for software in...

Page 97: ...rrupt nop nop nop brint return_enable 50 BSP receive interrupt nop nop nop bxint goto BXINT0 54 BSP transmit interrupt nop nop trint goto trint 58 TDM receive interrupt nop nop txint return_enable 5C TDM transmit interrupt nop nop nop int3 return_enable 60 external interrupt int3 nop nop nop hpiint goto hpiint 64 HPIint DO NOT MODIFY IF USING DEBUGGER nop nop space 24 16 68 7F reserved area ...

Page 98: ...0 asm1562 asm l mg q s pause asm500 c1562 cnv l mg q s pause lnk500 linker cmd Linker cmd File Linker lnk COMMAND FILE title COMMAND FILE FOR TLV1562 ASM This CMD file allocates the memory area for the TLV1562 interface Program stack 0x0080 M asm1562 MAP O asm1562 OUT v0 c l rts lib asm1562 obj c1562 obj MEMORY PAGE 0 VECT origin 0200h length 0080h PROG origin 0400h length 0300h PAGE 1 RAMB0 origi...

Page 99: ...ument to fit his specific applicaltion 10 References TLV1562 Data Sheet TMS320C54x Fixed Point Digital Signal Processor Data Sheet Literature number SPRS039B TMS320C54x DSP Algebraic Instruction Set Literature number SPRU179 TMS320C54x DSP Mnemonic Instruction Set Literature number SPRU172 TMS320C54x DSP CPU and Peripherals Literature number SPRU131D TMS320C54x Optimizing C Compiler Literature num...

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