Conversation Between the TLV1562 and the DSP
14
SLAA040
7.3
Mono Interrupt Driven Mode Using CSTART
Use the CSTART signal when two or more ADCs must sample/convert signals
at the same time. Instead of the RD signal, the timing for sampling and converting
is started with the edges of the CSTART signal. The RD signal is still required to
get the data out of the ADC and onto the bus.
Table 8. DSP Algorithm for Mono Interrupt Driven Mode Using CSTART
Wait cycles for the DSP internally (40MHz DSPCLK):
STEPS
TIMING, NOTES
APD=0
ADCSYCLK
= 7.5 MHz
APD=0
ADCSYCLK
= 10 MHz
APD=1
ADCSYCLK
= 10 MHz
APD=1
ADCSYCLK
= 10 MHz
1.
Set CS
Deselect ADC
2.
Clear CSTART
tTis starts sampling
3.
Wait for t
W(CSTARTL)
t
W(CSTARTL)
= 100 ns
(APD=0)
t
W(CSTARTL)
= 600 ns
(APD=1)
≥
4
≥
4
≥
24
≥
24
4.
Set CSTART
This starts the conversion
5.
Wait until INT goes low
Alternative: ignore the INT signal,
wait 14ns+5 ADCSYSCLK and goto
step number 7
≥
33
≥
21
≥
33
≥
21
6.
Wait the time t
D(INTL-CSI)
t
D(INTL-CSI)
= 10 ns
≥
1
≥
1
≥
1
≥
1
7.
Clear CS
Select the ADC
8.
Clear RD
Start communication
9.
Wait the time t
EN(DATAOUT)
t
EN(DATAOUT)
= 41 ns
≥
2
≥
2
≥
2
≥
2
10.
Read sample out from the data port;
Reset RD signal
11.
Set CS
Deselect ADC
12.
Go to step 2 for the next samples
Summary of Contents for TLV1562
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