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Figure 4-39. MLB Interface Connector

Table 4-23

lists the pinout for MLB Header J22 (QSH-020-01-L-D-DP-A).

Table 4-23. MLB Header Pinout

Pin No

Signal

Pin No

Signal

MLB0_MLBSIG_N

H_MLB0_MLBCLK

MLB0_MLBSIG_P

H_MLB0_MLBSIG

MLB0_MLBDAT_N

H_MLB0_MLBDAT

MLB0_MLBDAT_P

H_MLB0_REFCLK

MLB0_MLBCLK_N

MLB0_MLBCLK_P

DGND

MLB0_GPIO0

MLB_RSTz

I2C0_SCL

MLB_INT#

I2C0_SDA

VSYS_IO_3V3

VCC_12V0

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J721E EVM Hardware Architecture

SPRUIS4D – MAY 2020 – REVISED MARCH 2022

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Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)

Summary of Contents for TDA4VM

Page 1: ...mulation 23 4 J721E EVM Hardware Architecture 26 4 1 J721E EVM Hardware Top level Diagram 26 4 2 J721E EVM Interface Mapping 28 4 3 I2C Address Mapping 29 4 4 GPIO Mapping 30 4 5 Power Supply 31 4 6 Reset 38 4 7 Clock 39 4 8 Memory Interfaces 42 4 9 MCU Ethernet Interface 48 4 10 QSGMII Ethernet Interface 50 4 11 PCIe Interface 52 4 12 USB Interface 58 4 13 CAN Interface 61 4 14 FPD Interface Audi...

Page 2: ...15 MCU Gigabit Ethernet Block 48 Figure 4 16 MCU Ethernet PHY Settings 49 Figure 4 17 Quad SGMII Board I2C 51 Figure 4 18 QSGMII Ethernet PHY Settings 52 Figure 4 19 PCIe Interface for SERDES0 53 Figure 4 20 PCIe SMBUS Block Diagram 53 Figure 4 21 1L PCIe Root Complex Endpoint Selection Circuit 54 Figure 4 22 USB2 0 Header Connection 55 Figure 4 23 PCIe Interface for SERDES1 56 Figure 4 24 2L PCIe...

Page 3: ...ble 4 14 Reference Clock Selection for PCIe Endpoint Operation 54 Table 4 15 Resistors for Selecting PCIe Card Host or Device Operation 55 Table 4 16 Reference Clock Selection for PCIe Host Operation 57 Table 4 17 Reference Clock Selection for PCIe Endpoint Operation 57 Table 4 18 Resistors for Selecting PCIe Card Host or Device Operation 57 Table 4 19 FPD Audio Deserializer HSD Connector Pinout 6...

Page 4: ...de Infotainment Expansion Board Gateway Ethernet Switch Industrial GESI Expansion Board Fusion CSI2 Expansion Board s 1 1 Key Features The J721E EVM is a high performance standalone development platform that enables users to evaluate the Texas Instrument s Keystone III System on Chip SoC Below are the EVM s key features Processor J721E DRA829 TDA4xM 24 mm x 24 mm 0 8 mm pitch 827 pin FCBGA Support...

Page 5: ... 2x USB FTDI UART over USB 2x I3C headers 1x ADC Header Expansion Connectors to support application specific add on boards MLB MLBP Expansion Interface Image Video Capture Expansion Interface Apple Authentication Module Interface General Expansion Interface REACH and RoHS Compliant 1 2 Thermal Compliance There is elevated heat on the processor heatsink use caution particularly at elevated ambient ...

Page 6: ... 1 4 EMC EMI and ESD Compliance Components installed on the product are sensitive to Electrostatic Discharge ESD It is recommended this product be used in an ESD controlled environment This may include a temperature and or humidity controlled environment to limit the buildup of ESD It is also recommended to use ESD protection such as wrist straps and ESD mats when interfacing with the product The ...

Page 7: ...mera Module with serializer Expansion Fusion1 Serial Capture Board1 A Only one board can be connected to Expansion connector at a time B Only one board can be connected to CSI2 Expansion connector at a time Figure 2 2 System Architecture Interface The J721E EVM System on Module SoM board a Jacinto7 Common Processor board and Quad Port Ethernet Board Detailed descriptions of these cards are explain...

Page 8: ... 3 J721E EVM Board Identification SOM CPB QP Ethernet J721E EVM Overview www ti com 8 Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM SPRUIS4D MAY 2020 REVISED MARCH 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 9: ...4 LVCMOS Group 2 J3 LVCMOS Group 1 Power J5 DSI0 DP0 Hyper Flash Hyper RAM OSPI FLASH Figure 2 4 J721E SOM Component Identification www ti com J721E EVM Overview SPRUIS4D MAY 2020 REVISED MARCH 2022 Submit Document Feedback Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM 9 Copyright 2022 Texas Instruments Incorporated ...

Page 10: ...Flash User LEDs PCIe X2 Lane Socket PCIe X1 Lane Socket ENET EXP Mating Conn USB HUB EVM CONFIG SW UFS Memory APPLE AUTH HDR EXT Power Measurement HDR FAN HDR RESET PB MLB MLBP Header MCAN Headers FT2232 UART USB FT4232 UART USB SYS MCU BOOT Switches FPD Link Tuner Deserializer PCIe M 2 Socket 2280 Micro SD Card RGMII PHY Expansion Connectors Battery Holder FPD Link DSI Serializer DSI FPC Connecto...

Page 11: ...ce single DisplayPort interface is supported These interfaces are identified with a grey color in the component placement pictures opposed to the yellow color 2 4 Quad Ethernet Components Identification Stacked RJ45 SGMII Top P3 Bottom P2 Stacked RJ45 SGMII Top P1 Bottom P0 Quad SGMII PHY Clock Gen ENET EXP Mating Conn Figure 2 6 Quad Ethernet Component Identification www ti com J721E EVM Overview...

Page 12: ... Current 5000 mA Table 3 1 Recommended External Power Supply DigiKey Part No Manufacturer Manufacturer Part No SDI65 12 U P6 ND CUI Inc SDI65 12 U P6 SDI65 12 UD P6 ND CUI Inc SDI65 12 UD P6 EVM s 2 5 x 5 5 mm DC barrel jack connector J7 supports 10 A current rating Polarity outside barrel is Negative GND inside post is Positive PWR Figure 3 1 Connector Used for Power Input EVM User Setup Configur...

Page 13: ...To turn the board ON slide the switch in the direction as shown in Figure 3 2 ON Figure 3 2 Power ON OFF Switch www ti com EVM User Setup Configuration SPRUIS4D MAY 2020 REVISED MARCH 2022 Submit Document Feedback Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM 13 Copyright 2022 Texas Instruments Incorporated ...

Page 14: ...ion and power good LEDs are provided to indicate the power status Table 3 2 Power LED Status LED ON Status OFF Status LD2 Board Power on Board Power off LD3 Input voltage is 28 V or 6 V Input voltage is within the limit Figure 3 3 Power ON Fault LEDs EVM User Setup Configuration www ti com 14 Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM SPRUIS4D MAY 2020 REVISED MARCH 2022 Submit Document Fe...

Page 15: ...connectors The power good signals of these power regulators are used to generate the SoC PORz Multiple power indication LEDs are provided on board to give users positive confirmation of the status of output of major supplies The LEDs indicated power in the various domains Table 3 3 Power LEDs Sl No LED Power Status Sch Net Name 1 LD2 Input Power On Off VINPUT 2 LD7 Regulated Power On Off VSYS_3V3 ...

Page 16: ... 12 0V VSYS_3V3 TP130 3 3V VCC_12V0 TP39 12 0V VSYS_5V0 TP26 5 0V EXP_3V3 TP43 3 3V VDD_2V5 TP63 2 5V VDD_1V0 TP59 1 0V VCC_1V1 TP60 1 1V VSYS_MCU_5V0 TP117 5 0V VDD_SD_DV TP44 3 3V VSYS_MCUIO_3V3 TP113 3 3V VSYS_IO_3V3 TP131 3 3V VSYS_MCUIO_1V8 TP134 1 8V VSYS_IO_1V8 TP132 1 8V VDA_MCU_1V8 TP105 1 8V EVM User Setup Configuration www ti com 16 Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM SPR...

Page 17: ...U_RESETz MCU domain Warm Reset input 3 SW4 PORz Main domain Power on Reset input 4 SW6 RESET_REQz Main domain Warm Reset input 5 SW10 SOC_EXTINTn External Interrupt input 6 SW11 SYS_IRQz System IRQ Interrupt input also used as SYS_WAKE 7 SW12 MCAN0_WAKE CAN Wakeup Input SW10 EXTINTn SW11 SYS_IRQz SW12 CAN_WK RESET PUSH BOTTOMS Figure 3 5 EVM Push Buttons www ti com EVM User Setup Configuration SPR...

Page 18: ...pherals Some of the configuration is for peripherals on the CPB while others switches are used to configure peripherals on Expansion Boards For those settings the device specific Expansion Board User s Guide will define the switch function Figure 3 6 EVM Configuration DIP Switch EVM User Setup Configuration www ti com 18 Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM SPRUIS4D MAY 2020 REVISED ...

Page 19: ...terface Mode Select supports port PCIe0 0 OFF Root Complex 1 ON End Point SW3 6 OFF PCIe_2L_MODE_SEL PCIe 2 Lane Mode Select supports port PCIe1 0 OFF Root Complex 1 ON End Point SW3 7 ON CSI_VIO_SEL Sets I O voltage for CSI2 Expansion Interface LVCMOS signals 0 OFF 1 8V I O Voltage 1 ON 3 3V I O Voltage SW3 8 ON INFO_CAM_VIO_SEL Switch is to be used on Expansion board See specific expansion board...

Page 20: ...watchdog timer control is set with SW2 2 1 ON PMIC I O used for GPIO8 test point SW2 2 ON LEOA_WDOG_DIS Enable Disable selection for PMIC Watchdog Timer 0 OFF PMIC watchdog timer is enabled 1 ON PMIC watchdog timer is disabled note requires SW2 1 to be set to OFF SW3 1 ON SOC_SAFETY_ERRz Option to combine SOC_SAFETY_ERRz with MCU_SAFETY_ERR and PMIC 0 OFF SOC_SAFETY_ERRz Main is isolated from PMIC...

Page 21: ... 1K 1 TP135 1 4 R3 5 R362 1 4 C618 0 1uF 50V R316 1K 1 U151 SN74LVC1G08DBVRE4 1 2 4 3 5 R3 4 1 4 1 4 R361 R323 1K 1 R329 1K 1 C645 0 01uF 25V C616 0 1uF 50V C619 0 1uF 50V 1 4 R371 R360 1 4 R328 1K 1 1 4 R37 U147 TCA6424ARGJR P00 1 P01 2 P02 3 P03 4 P04 5 P05 6 P06 7 P07 8 P20 17 P21 18 P22 19 P23 20 P24 21 P25 22 P26 23 P27 24 25 GND ADDR 26 27 VCCP RESET 28 SCL 29 SDA 30 31 VCC INT 32 P10 9 P11 ...

Page 22: ...r can establish a Virtual Com Port that can be used with any terminal emulation application The FT2232H is bus powered Virtual Com Port drivers for the FT4232H can be obtained from https www ftdichip com Products ICs FT2232H html RS232 hardware control feature is supported on MCU UART0 Both FT2232H and FT4232H circuits powered through USB VBUS Since the circuits are powered through BUS power the c...

Page 23: ...C_EMU0 SOC_EMU1 EXT_MIPI_TDI EXT_MIPI_TMS EXT_MIPI_TCK EXT_MIPI_TRST EXT_MIPI_TDO EXT_MIPI_EMU0 EXT_MIPI_EMU1 ExternalJTAG XDS110_TDI XDS110_TMS XDS110_TCK XDS110_TRST XDS110_TDO XDS110_EMU0 XDS110_EMU1 OnboardJTAG Figure 3 8 JTAG Mux Table 3 11 JTAG 1 2 Mux selection Condition MUX_SEL Function XDS110 Powered via USB HIGH A B2 port On Board EMU External Emulator attached LOW A B1 port EXTERNAL EMU...

Page 24: ...IO_3V3 31 TRC_DATA6 2 MIPI_TMS 32 NC 3 MIPI_TCK 33 TRC_DATA7 4 MIPI_TDO 34 NC 5 MIPI_TDI 35 TRC_DATA8 6 MIPI_TGTRST 36 NC 7 MIPI_RTCK 37 TRC_DATA9 8 MIPI_TRST_PD EXT_MIPI_TRST 38 EXT_MIPI_EMU0 9 MIPI_nTRSTPU 39 TRC_DATA10 10 NC 40 EXT_MIPI_EMU1 11 NC 41 TRC_DATA11 12 VSYS_IO_3V3 42 NC 13 TRC_CLK 43 TRC_DATA12 14 NC 44 NC 15 DGND 45 TRC_DATA13 16 DGND 46 NC 17 TRC_CTL 47 TRC_DATA14 18 TRC_DATA19 48...

Page 25: ... 4 MIPI_20_TDIS 14 MIPI_20_EMU1 5 MIPI_20_VTREF 15 SYSRST 6 NC key 16 DGND 7 MIPI_20_TDO 17 NC 8 20PJTAG_DET 18 NC 9 MIPI_20_RTCK 19 NC 10 DGND 20 DGND Table 3 14 TI14 Pin Connector J2 Refer PROC081E2 SCH Pinout Pin No Signal Pin No Signal 1 MIPI_14_TMS 8 14PJTAG_DET 2 MIPI_14_TRST 9 MIPI_14_RTCK 3 MIPI_14_TDI 10 DGND 4 MIPI_14_TDIS 11 MIPI_14_TCK 5 MIPI_14_VTREF 12 DGND 6 NC key 13 MIPI_14_EMU0 7...

Page 26: ...op level Diagram Figure 4 1 shows the functional block diagram of the J721E EVM Figure 4 1 J721E EVM Functional Block Diagram J721E EVM Hardware Architecture www ti com 26 Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM SPRUIS4D MAY 2020 REVISED MARCH 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 27: ...ator CDCI6214 I2C0_SCL I2C0_SDA VOLTAGE REGULATOR TPS74801 x2 3 3 V 2 5 V 1 V POWER 12 V 5 V 3V3 STACKED RJ45 WITH INTEGRATED MAGNETICS X2 LPJG17512AONL Port 1 Port 2 Port 3 Port 4 Figure 4 2 Quad Port Ethernet Expansion Functional Block diagram www ti com J721E EVM Hardware Architecture SPRUIS4D MAY 2020 REVISED MARCH 2022 Submit Document Feedback Jacinto7 J721E DRA829 TDA4VM Evaluation Module EV...

Page 28: ...B 3 1 Type C PD CC Controller SERDES3 USB0 2012670005 PTPS25830QWRHBTQ1 TUSB321RWBR USB 2 0 HUB USB1 TUSB4041IPAPR Display Port SERDES4 DP0 472720001 FPD Link Panel Serializer DSI0 PDS90UB941ASRTDTQ1 FPD Link Radio Tuner McASP11 DS90UB926QSQE Audio Codec McASP10 PCM3168APAP PCIe x4 Lane Socket x1 Lane SERDES0 PCIe0 10142333 10111MLF PCI2 x4 Lane Socket x2 Lane SERDES1 PCIe1 10142333 10111MLF PCIe ...

Page 29: ...0x20 EVM CPB SoC_I2C0 24 bit I2C GPIO Expander 2 TCA6424ARGJR 0x21 EVM CPB SoC_I2C0 I2C MUX for both x2LANE and x1LANE PCIe Interface TCA9543APWR 0x70 EVM CPB SoC_I2C0 I2C MUX for M 2 PCIe Connector 2 L PCIe Gen4 SERDES2 TCA9543APWR 0x71 EVM CPB SoC_I2C0 MLB Physical Interface Board connector interface EXP QSGMII SoC_I2C0 Clock Generator on Quad ENET Board CDCI6214 TBD EVM CPB SoC_I2C1 8 bit I2C G...

Page 30: ...rmal operation 1 system power down MCU_SPI0_ D1 WKUP_ GPIO0_54 MCU_CAN0_STBz Output PD Active low MCU CAN0 Standby Main Domain EXTINTN GPIO0_0 SOC_EXTINTN Input PU Active low Push button Interrupt User Defined RGMII6_RX_ CTL GPIO0_98 C_MCASP10_ AFSR NA PU Active low I2C0 I O expander interrupt 0 interrupt pending 1 no interrupt I2C0_IOEXP_INT Note GPIO only available from Trace GPMC Mux RGMII6_ RD...

Page 31: ...olution which is optimized for the J721E to support a wide variety of use cases Dual load switch TPS22976 Q1 provides the switching option for the LPDDR4 I O power supply 1 1 V 0 6 V Figure 4 3 J721E SOM Power Distribution Block Diagram www ti com J721E EVM Hardware Architecture SPRUIS4D MAY 2020 REVISED MARCH 2022 Submit Document Feedback Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM 31 Copy...

Page 32: ...S014 USB 3 0uAB IN EN IN VS VCC_12V0 VOUT Reverse polarity protection circuit PG 2 LOAD SW TPS1H100A IN VS VIN USBC_PWR_EN USB1_DN1_PE USB1_DN2_PE LOAD SW TPD3S014 USB2 0 TYPE A CONN IN EN DP1_PWR_SW_EN DP0_PWR_SW_EN EN2 CSI_VIO_SEL USB2_DRVVBUS VSYS_IO_3V3 PWR_SW_CNTL_DSI0 R UB926_PWR_SW_CNTRL TA_PORZ PMIC_PORz PCIe1_PORz PCIe0_PORz PORz R VSYS_IO_3V3 EN Pull down with resistor regulators switch ...

Page 33: ...rvisor devices are provided to monitor Main power input and VSYS_3V3 Figure 4 5 Voltage Supervisor Circuit www ti com J721E EVM Hardware Architecture SPRUIS4D MAY 2020 REVISED MARCH 2022 Submit Document Feedback Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM 33 Copyright 2022 Texas Instruments Incorporated ...

Page 34: ...ch SW1 Bit 1 provides an option to change the logic of D Flip Flop U7 that controls the Load Switches TPS22965TDSGRQ1 and TPS22976NDPUT to decide the I O supply voltages Table 4 4 DDR I O Voltage Selection SW1 Bit 1 SDRAM_TYPE Selected DDR I O Voltage LOW LPDDR4X 0 6V HIGH LPDDR4 1 1V Figure 4 6 LPDDR4 IO Voltage Selection Circuit J721E EVM Hardware Architecture www ti com 34 Jacinto7 J721E DRA829...

Page 35: ... and write to clear the ENABLE_INT interrupt 0x65 1 0x1 ENABLE_INT The EVM can be woke from the low power state by pressing the CAN_WAKEn button SW12 4 5 3 2 J721E SoC MCU Only Operation Table 4 6 J721E SoC S2R Logic Flow Leo PMIC Transition From Active Mode to S2R Mode Action Address Bits Data Register Bit Names Unmask GPIO10_RISE MASK on LeoA I2CID 0x48 0x51 4 0x0 GPIO10_RISE_MASK Read and write...

Page 36: ...V_SRC VDDR_IO_DV SOC_I2C2 PM1 0x4A 0 01E VDD_CORE_0V8_REG VDD_PHYCORE_0V8 SOC_I2C2 PM1 0x4B 0 01E VDA_PLL_1V8_REG VDA_PLL_1V8 SOC_I2C2 PM1 0x4C 0 01E VDD_PHYIO_1V8_REG VDD_PHYIO_1V8 SOC_I2C2 PM1 0x4D 0 01E VDA_USB_3V3_REG VDA_USB_3V3 SOC_I2C2 PM1 0x4E 0 01E SPARE NA SOC_I2C2 PM1 0x4F NA VDD_MCUIO_1V8_REG VDD_IO_1V8 SOC_I2C2 PM2 0x40 0 01E VSYS_3V3 VDD_IO_3V3 SOC_I2C2 PM2 0x41 0 01E VDD_SD_DV_REG V...

Page 37: ... is provided from SYS_PWR_PG which is enabled by default on power up External Power Monitor header details Mfr Part 68002 205HL CON HDR 1X5 2 54MM PITCH ST TH Table 4 8 External Power Monitor Header Pinouts Header J12 Pin Number Signal Name 1 CON_PM1_SCL 2 CON_PM1_SDA 3 DGND 4 CON_PM2_SDA 5 CON_PM2_SCL Test automation header on the Common processor board also can access these INA devices externall...

Page 38: ...rchitecture Figure 4 7 EVM Reset Architecture J721E EVM Hardware Architecture www ti com 38 Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM SPRUIS4D MAY 2020 REVISED MARCH 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 39: ...L937 Q1 1 8V 25MHz XTAL MCU RGMII PHY R R 25MHz REF XTAL 25MHz REF XTAL 25MHz REF XTAL 22 5792MHz GESI INFO EXPANSION RGMII USB HUB TUSB4041 DSI TO FPD BRIDGE 24MHz XTAL R R XTAL R R 25MHz 24MHz 25MHz CSI2 EXPANSION 25MHz CP Board LVL TXLR GESI INFO EXPANSION SPARE 25MHz 100MHz P N SERDES3 RTC Module 32 768KHz XTAL R R From CP board RTC Module Figure 4 8 EVM Clock Architecture EVM supports multipl...

Page 40: ...cessor Both WKUP_LFOSC and OSC1 are optional clocks not required for J721E processing The WKUP_LFOSC can be sourced either on the on board crystal or from the PMIC The OSC1 can be sourced from either the on board crystal or from clock generator CDCEL937 on the Common Processor board J721E EVM Hardware Architecture www ti com 40 Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM SPRUIS4D MAY 2020 R...

Page 41: ...R160 R159 CDCI2 Y2 100 MHz HCSL Clock to SoC USB 100 MHz QSGMII_PHY_REFCLK_P N C108 C109 CDCI2 Y3 125 MHz LVDS Clock to Ethernet Expansion board 125 MHz CLKGEN_PCIE2_2L_REFCLK_P N R123 R124 CDCI2 Y4 100 MHz HCSL Clock to PCIe M 2 Socket 100 MHz The PCIe reference clocks to the PCIe x1 x2 and M 2 sockets are also derived from the CDCI clock generators 4 7 3 EVM Peripheral Ref Clock The reference cl...

Page 42: ...240 DDR_DQ 31 24 DDR_DM3 DDR_DQS3P DDR_DQS3N DDR_DQ 23 16 DOR_DM2 DDR_DQS2P DDR_DQS2N DDR0_CSN0_1 DDR0_CSN1_1 DDR0_CKE1 DDR_DQ 15 8 DDR_DM1 DDR_DQS1P DDR_DQS1N DDR_DQ 7 0 DDR_DM0 DDR_DQS0P DDR_DQS0N DDR0_CA 5 0 DDR0_CSN0_0 DDR0_CSN1_0 DDR0_CKE0 DDR0_CK_T DDR0_CK_C DDR0_RESETn DDR0_CAL DDR_RET VDD2 VDD2 VDDQ ZQ ODTCA_A1 ODTCA_B1 DQ 15 8 _B DM 1 _B DQS 1 _t_B DQS 1 _c_B DQ 7 _B DM 0 _B DQS 0 _t_B DQ...

Page 43: ...1KS512SC0 which is a 512 Mb flash 64 Mb DRAM 12 bit Active mux TS3DDR3812RUAR is provided to select either OSPI or HBMC interface The selection of OSPI and hyper flash will be done by using a DIP SW3 switch that is populated on the CP board For more information see Section 3 4 1 OSPI Hyper Flash Figure 4 11 J721E SoM OSPI and Hyper Flash www ti com J721E EVM Hardware Architecture SPRUIS4D MAY 2020...

Page 44: ...ort of SoC The UFS memory is Gear3 2Lane capable and supports UFS Version 2 1 Figure 4 12 UFS Memory Block Diagram J721E EVM Hardware Architecture www ti com 44 Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM SPRUIS4D MAY 2020 REVISED MARCH 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 45: ... SoC The flash is connected to 8 bits of the MMC0 interface supporting HS400 double data rates up to 200 MHz External pull up resistors 49 9K are provided on DATA 7 0 CMD and Reset signals pull down resistor is provided on the data strobe signal to prevent bus floating Figure 4 13 eMMC Memory Block Diagram www ti com J721E EVM Hardware Architecture SPRUIS4D MAY 2020 REVISED MARCH 2022 Submit Docum...

Page 46: ... controlled by the processor s I2C0 port I2C address of the I O expander is 0x22 J7E21E SOM VDD_SD from PMIC MMC1_SDCD Micro SD CARD CONN DM3BT DSF PEJS VDD_SD 3V3 From GPIO Expander EN Load Switch TPS22918DB 3V3 VDD_MMC1 22 MMC1_CLK MMC1_CMD MMC1_DAT 0 3 47N Ÿ ESD TPD2E001DRLR ESD TPD2E001DRLR VDD_MMC1 Figure 4 14 micro SD Card Block Diagram An ESD protection device Mfr Part TPD2E001DRLR is provi...

Page 47: ...Payload type Length 2 Offset to next header Board_Name 16 Name of the board Design_Rev 2 Revision number of the design PROC_Nbr 4 PROC number Variant 2 Design variant number PCB_Rev 2 Revision number of the PCB SCHBOM_Rev 2 Revision number of the schematic SWR_Rev 2 First software release number VendorID 2 Build_Week 2 Week of the year of production Build_Year 2 Year of production BoardID 6 Serial...

Page 48: ...sing a crystal to DP83867ERGZT Figure 4 15 MCU Gigabit Ethernet Block The I O supply to the Ethernet PHY is set through selection Resistors R445 and R446 to support both 1 8 V and 3 3 V I O level The EVM is configured to 3 3 V I O supply for MCU RGMII PHY I O signals by default J721E EVM Hardware Architecture www ti com 48 Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM SPRUIS4D MAY 2020 REVISE...

Page 49: ...ted to the RX data and control pins that are normally driven by the PHY and are inputs to the processor The voltage range for each mode is shown below Mode 1 0V to 0 3V Mode 2 0 462 V to 0 6303 V Mode 3 0 7425 V to 0 9372 V Mode 4 2 2902 V to 2 9304 V These are the defaults set for the MCU RGMII PHY ADDR 00000 Auto_neg Enabled ANGsel 10 100 1000 RGMII Clk skew Tx 0 ns RGMII Clk skew Rx 2 ns The st...

Page 50: ... default Optionally clock generator on the Quad Port Ethernet board also can provide the clock to the PHY with resistor option Table 4 12 Clock Source Selection Clock Source Install Remove From CP Board Default R1 R2 R3 R4 From On board clock generator R3 R4 R1 R2 Programming of the clock generator is done through I2C0 port of the SoC I2C signals to the on board clock generator is connected throug...

Page 51: ...re 4 17 Quad SGMII Board I2C Coupling capacitors 0 1 µF added in series at the respective driver ends on the QSGMII data signals The address and clock configurations are shown below PHY0 10000 0X10 PHY1 10001 0X11 PHY2 10010 0X12 PHY3 10011 0X13 www ti com J721E EVM Hardware Architecture SPRUIS4D MAY 2020 REVISED MARCH 2022 Submit Document Feedback Jacinto7 J721E DRA829 TDA4VM Evaluation Module EV...

Page 52: ...des one x4 lane PCIe connector of part number Amphenol 10142333 10111MLF which supports PCIe Gen4 operation The pin out of the connector follows PCIe standard The SERDES0 port of J7 SoC is connected to x1 lane PCIe socket for data transfer PCIe0 USB0_SS and SGMII1 2 interfaces are pinmuxed with this SERDES0 port I2C0 from SoC is used for control purpose and is connected to SMBUS on the connector I...

Page 53: ...3 V J8 U15 3 3 V J11 SOC_I2C0_SDA SOC_I2C0_SCL I2CADD 0x70 Figure 4 20 PCIe SMBUS Block Diagram www ti com J721E EVM Hardware Architecture SPRUIS4D MAY 2020 REVISED MARCH 2022 Submit Document Feedback Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM 53 Copyright 2022 Texas Instruments Incorporated ...

Page 54: ...e through resistors as shown in Table 4 13 Table 4 13 Reference Clock Selection for PCIe Host Operation Clock Selected Mount Unmount Reference Clock for SOC from clock generator R194 R195 C92 R198 R199 C93 Reference Clock for PCIe connector from SOC R195 C92 R194 R109 R199 C93 R198 R110 Reference Clock for PCIe connector from clock generator R109 R195 C92 R110 R199 C93 For PCIe Endpoint operation ...

Page 55: ...unt Demount Host mode R674 R675 R679 Device mode R675 R674 R679 Additional Options Optional MDIO bus and USB2 0 interface is supported for external PCIe add on cards SoC Main domain CPSW9G0 MDIO signals are interfaced to the x1L PCIe Socket J11 through 0 Ω inline resistors R137 and R136 when network Ethernet based add on cards inserted into J11 The path is disconnected by default Also USB2 0 data ...

Page 56: ...T from both the X1 and X2 lane PCIe connectors is terminated to I2C switch Reset A dip Switch SW3 is provided to select the reset source for host and end point PCIe operation In case of host mode signal from GPIO Expander and PORz signals from SoC are ANDed and the output is connected to PCIe connector The GPIO signal is pulled low to ensure PCIe Reset PERST remains asserted until SoC releases res...

Page 57: ...ock Selection for PCIe Endpoint Operation Clock Selected Mount Unmount Reference clock for SOC from clock generator R214 R211 C44 R213 R210 C51 Reference clock for SOC from PCIe connector R211 C44 R214 R54 R210 C51 R213 R56 Hot plug The PRSNT1 and PRSNT2 signals are the hot plug presence detect signals The PRSNT1 is pulled up and PRSNT2 is connected to GPIO expander so that PRSNT1 will be pulled l...

Page 58: ...PIO expander The GPIO signal is pulled low with a resistor 10K by default to ensure PCIe Reset PERST remains asserted until SoC releases reset Clock A clock generator CDCI 2 is provided to drive 100MHz HCSL clock for PCIe add on cards and J721E SoC Resistor options are provided to select the clock source either from SoC or clock generator 4 12 USB Interface The Common Processor Board includes the ...

Page 59: ...provided on TX lines of Super speed signals and common mode filters MCZ1210DH900L2TA0G are used at all the differential pairs ESD protection diodes are provided on all required USB Signals TPD1E05U06DPY for super speed signals and TPD2E2U06 Q1 for CC pins TUSB321 s Current Mode pin is pulled high through 499K resistor to set the Maximum Current Iout to 1 5A Iout max 1 5A Figure 4 27 Type C Power D...

Page 60: ...pheral clock generator using a resistor mux The default clock source is set to crystal Figure 4 28 USB Hub Reference Clock Circuit Figure 4 29 shows the USB HUB strapping options 1 2 3 4 1 2 3 4 NOTE Automatic Charge Mode Disabled PWRCTL Polarity is Active High Power Switching and Overcurrent Inputs Supported Individual Power Control Enabled Figure 4 29 USB Hub Settings Circuit And the USB ID pin ...

Page 61: ...e Common Processor board as explained below MCU CAN0 The MCU CAN0 port of J721E SoC is connected to the CAN transceiver with Wake function supported device TCAN1043 Q1 A 2 pin header J29 68002 202HLF is provided inline for user probe option The output of the CAN transceiver is terminated to a 4 pin header J30 61300411121 The signals MCU_MCAN0_H and MCU_MCAN0_L are routed as differential signals wi...

Page 62: ...h Wake function supported device TCAN1043 Q1 A 2 pin header J24 68002 202HLF is provided inline for user probe option The output of the CAN transceiver is terminated to a 4 pin header J27 61300411121 The signals MCAN0_H and MCAN0_L are routed as differential signals with 120E impedance with split termination The STB signal is an active low signal held low with integrated pull down by default The V...

Page 63: ...ls MCAN2_H and MCAN2_L are terminated to a 3 pin header J28 68001 403HLF with 120E split termination The STB signal is an active High signal held high with external pull up by default The GPIO control from MAIN domain provided to pull the line low To interface these CAN signals to Test system the below given custom converter to be prepared Figure 4 33 CAN Header Connections to DB9 Test Instrument ...

Page 64: ...b I2C Address R1 R2 0x2C Open 40 2K other see DM Figure 4 34 FPD Link UB926 ID Setting Circuit Power 12 V is provided to the HSD connector using a power switch TPS1H100AQPWPRQ1 to power the FPD Link III Tuner expansion board The power switch is controlled by a GPIO expander signal UB926_PWR_SW_CNTRL Figure 4 35 shows the mode selection for the de serializer MODE Selection See R3 in table See R4 in...

Page 65: ...provided on ID X pin to set the 7 b I2C address to 0x16 The device Alias ID and the Mode selection is set by hardware strap resistors as shown in Figure 4 36 Mode SEL0 3 Mode SEL1 4 Splitter 0 DSI lanes 4 Non Cont Clk 1 Coax 0 STP DSI Disable 0 7b I2C Address 0x16 default R1 R2 16 2K 40 2K other see DM R3 R4 R5 R6 See R1 in table See R2 in table MODE Selection DEVICE ALIAS ID UB941A_MODE_SEL0 UB94...

Page 66: ...r I2C3 interface Default I2C address is set to 0x44 The device reset is controlled by the I2C GPIO expander using a I2C3 master port Line IN Port Single ended Stereo 1x Line Input signal from the Audio Jack J38 is converted to differential using single ended to differential converter with Anti aliasing low pass fiter and interfaced with CODEC MIC Input Port Single ended Stereo 2x MIC Input signals...

Page 67: ...e OUT and 3x Head Phone OUT 1x Standard 3 5mm Stereo Audio Jack Mfr Part SJ 3524 SMT TR provided for 1x Line IN interface MIC L VIN1 MIC R VIN2 HPOUT L VOUT1 HPOUT R VOUT2 HPOUT L VOUT5 HPOUT R VOUT6 Line IN L VIN5 Line IN R VIN6 MIC L VIN3 MIC R VIN4 Line OUT L VOUT7 Line OUT R VOUT8 HPOUT L VOUT3 HPOUT R VOUT4 Figure 4 37 Audio Port Interface Assignment www ti com J721E EVM Hardware Architecture...

Page 68: ...DP1_AUXP DP1_AUXN VSYS_3V3 VSYS_3V3 V3V3_DP0 V3V3_DP1 Figure 4 38 Display Port Block Diagram Separate ESD protection devices of Mfr Part TPD1E05U06DPY are used for main and auxiliary data channels and Common mode filters MCZ1210DH900L2TA0G at every differential data and aux pairs Supply 3 3 V 500 mA for each connector has been given through individual LDOs Mfr Part TPS74801DRCR The LDO has active ...

Page 69: ...LBDAT_P 12 NC 13 NC 14 NC 15 NC 16 H_MLB0_REFCLK 17 MLB0_MLBCLK_N 18 NC 19 MLB0_MLBCLK_P 20 NC 21 DGND 22 DGND 23 NC 24 MLB0_GPIO0 25 MLB_RSTz 26 NC 27 NC 28 NC 29 NC 30 NC 31 NC 32 NC 33 I2C0_SCL 34 MLB_INT 35 I2C0_SDA 36 NC 37 VSYS_IO_3V3 38 VSYS_IO_3V3 39 VSYS_IO_3V3 40 VCC_12V0 www ti com J721E EVM Hardware Architecture SPRUIS4D MAY 2020 REVISED MARCH 2022 Submit Document Feedback Jacinto7 J72...

Page 70: ...inouts Table 4 24 MCU I3C Header J33 Pinout Pin No Signal 1 DGND 2 MCU_I3C0_SDA 3 MCU_I3C0_SCL Table 4 25 MAIN I3C Header J32 Pinout Pin No Signal 1 DGND 2 MCU_I3C0_SDA 3 MCU_I3C0_SCL 4 21 ADC Interface MCU ADC0 port of J721E SoC is interfaced to 2x10 header Mfr Part TSW 110 07 S D on Common Processor board The ADC inputs MCU_ADC0_AIN 7 0 and external Trigger input MCU_ADC_EXT_TRIGGER0 is connecte...

Page 71: ...wered by 3 3 V and a battery holder BC501SM is connected to VBAT pin for external battery power option battery not provided A 32 768 kHz quartz crystal is used to provide clock for the device MFP pin of RTC module is used to generate optional reference clock to the SoC s WKUP_LFOSC 7 bit I2C addresses are 0x57 and 0x6F J721E SOM MCP79410 MFP VBAT I2C0_SCL I2C0_SDA RTC_REF_CLK BC501SM VSYS_IO_3V3 B...

Page 72: ... have a 2 54 mm Dual row 10 Pin Receptacle Mfr Part 2214BR 10G I2C0 Port of J721E SoC and Reset from GPIO Expander is terminated to this connector 3 3 V supply is provided to the connector J9 Table 4 27 lists detailed signal and pin descriptions Table 4 27 APPLE AUTH Header J9 Pinout Pin No Signal Description 1 I2C0_SCL I2C slave interface clock connection 3 I2C0_SDA I2C slave interface data conne...

Page 73: ...low 8 VSYS_IO_3V3 Power 3 3 V 1 9 DGND Ground 3 4 5 NC Not Connected 4 24 EVM Expansion Connectors The Common processor board includes an Expansion connector of QSH 060 01 L D A K with 5mm mating height allowing multiple expansion boards Infotainment or GESI Expansion to be stacked below the processor board Either Infotainment or GESI Expansion board can be plugged into EVM expansion connectors J4...

Page 74: ...0_DATA1 PRG1_RGMII2_RD1 44 VOUT0_DATA20 PRG1_RGMII1_TX_CTL 45 VOUT0_DATA3 PRG1_RGMII2_RD3 46 VOUT0_DATA18 PRG1_RGMII1_TD2 47 VOUT0_DATA4 PRG1_RGMII2_RX_CTL 48 VOUT0_DATA21 PRG1_RGMII1_TXC 49 VOUT0_DATA6 PRG1_RGMII2_RXC 50 VOUT0_DATA17 PRG1_RGMII1_TD1 51 DGND 52 DGND 53 MCASP0_AXR5 MCAN9_TX 54 VPFE0_DATA12 PRG1_MDIO0_MDC 55 MCASP0_AXR6 MCAN9_RX 56 VPFE0_DATA11 PRG1_MDIO0_MDIO 57 MCASP0_ACLKX SPI3_C...

Page 75: ..._MDC I2C5_SDA 99 MDIO0_MDIO 100 PRG0_MDIO0_MDIO I2C5_SCL 101 SPI3_D0 102 MCASP0_AXR13 PRG0_PWM0_B2 103 SPI3_D1 104 NC 105 SPI3_CLK 106 RGMII_REFCLK 107 DGND 108 DGND 109 I2C0_SCL 110 MCASP1_ACLKX 111 I2C0_SDA 112 SOC_I2C2_SCL 113 I2C1_SCL 114 SOC_I2C2_SDA 115 I2C1_SDA 116 NC 117 NC 118 EXP_RSTz 119 DGND 120 DGND www ti com J721E EVM Hardware Architecture SPRUIS4D MAY 2020 REVISED MARCH 2022 Submit...

Page 76: ... EXP_MUX3 37 NC 38 NC 39 DGND 40 DGND 41 GPMC0_A1 42 GPMC0_A22 43 GPMC0_A2 44 GPMC0_DIR 45 GPMC0_A3 46 GPMC0_A17 47 GPMC0_A4 48 GPMC0_BE1 49 GPMC0_A5 50 GPMC0_A16 51 GPMC0_A7 52 GPMC0_A21 53 GPMC0_A6 54 GPMC0_A15 55 GPMC0_A9 56 GPMC0_A20 57 GPMC0_A11 58 GPMC0_A14 59 GPMC0_A8 60 GPMC0_A18 61 GPMC0_A10 62 GPMC0_A19 63 GPMC0_A12 64 GPMC0_A13 65 NC 66 NC 67 DGND 68 DGND 69 NC 70 NC 71 NC 72 NC 73 NC 7...

Page 77: ...ilizes power from Common processor board through expansion connector and it has two Low Drop Out circuits to supply Quad Port SGMII PHY with the necessary voltage and the power required Test points for each power outputs are provided on the Ethernet Expansion card and are mentioned in Table 4 31 Table 4 31 ENET Expansion Board Power Test Points Sl No Power Supply Test Point Voltage Tolerance Card ...

Page 78: ...et Expansion Board is used to remove the address conflict by either connecting any one of the clock generators Figure 4 44 CDCI I2C Isolation Circuit Set the CDCI_I2C_SEL I O EXP bit high to connect the I2C bus to the CDCI for programming on the Quad Port Ethernet Expansion Board During this time the CDCI device U17 on the Common Processor board should be in reset mode J721E EVM Hardware Architect...

Page 79: ...rface J10 Pin No Signal 1 DGND 2 NC 3 NC 4 DGND 5 NC 6 NC 7 DGND 8 NC 9 NC 10 DGND 11 VSYS_IO_3V3 12 VSYS_IO_3V3 13 DGND 14 EEPROM_A0 15 EEPROM_A1 16 EEPROM_A2 17 DGND 18 EEPROM_WP 19 REFCLK_25MHZ 20 DGND 21 WKUP_I2C0_SCL 22 WKUP_I2C0_SDA 23 DGND 24 I2C0_SCL 25 I2C0_SDA 26 DGND 27 VCC_12V0 28 VCC_12V0 29 DGND 30 ENET_EXP_PWRDN 31 QSGMII_INTN 32 DGND 33 QSGMII4_TX_P 34 QSGMII4_TX_N 35 DGND 36 QSGMI...

Page 80: ...rface The VC8514 device includes three external PHY address pins PHYADD 4 2 to allow control of multiple PHY devices on a system board sharing a common management bus These pins set the most significant bits of the PHY address port map The lower two bits of the address for each port are derived from the physical address of the port 0 to 3 and the setting of the PHY address reversal bit in register...

Page 81: ... CSI2 port of future J7 SoC Power 12 V and 3 3 V control GPIOs and reference clock to these CSI expansion boards are provided from Common Processor board through CSI expansion connector Optionally auxiliary 12 V can be supplied from Common Processor board via terminal block 1757242 using external wire The I O supply to these CSI expansion boards can be configured for both 3 3 V and 1 8 V using the...

Page 82: ...O2_DV 38 VCC_CSI_IO 19 CSI0_RX2_N 39 CSI1_RX2_N 20 CSI2_A_GPIO3_DV 40 VCC_CSI_IO Table 4 34 CSI Expansion Connector J48 Pinout CSI2 Connector Interface J48 Pin No Signal Pin No Signal 1 VCC_12V0 21 CSI2_RX3_P 2 CSI2_I2C_SCL_DV 22 CSI2_B_GPIO4_DV 3 VCC_12V0 23 CSI2_RX3_N 4 CSI2_I2C_SDA_DV 24 DGND 5 CSI2_RXCLK_P 25 NC 6 NC 26 NC 7 CSI2_RXCLK_N 27 NC 8 CSI2_B_GPIO1_DV 28 NC 9 CSI2_RX0_P 29 NC 10 CSI2...

Page 83: ...rsion Changes from Revision C February 2022 to Revision D March 2022 Page Updated EMC EMI and ESD Compliance section 6 www ti com Revision History SPRUIS4D MAY 2020 REVISED MARCH 2022 Submit Document Feedback Jacinto7 J721E DRA829 TDA4VM Evaluation Module EVM 83 Copyright 2022 Texas Instruments Incorporated ...

Page 84: ...o change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you will fully indemn...

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