Texas Instruments TAS3002 Data Manual Download Page 9

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2−2

2.2

Digital Output Modes

The digital output modes (SDOUT1, SDOUT2, SDOUT0) are described in Sections 2.2.1 through 2.2.3.

2.2.1

MSB-First, Right-Justified, Serial-Interface Format

The normal output mode for the MSB-first, right-justified, serial-interface format is for 16, 18, 20, or 24 bits. Figure 2−1
shows the following characteristics of this protocol:

•

Left channel is transmitted when LRCLK is high.

•

The SDIN(s) (recorded) data is justified to the trailing edge of the LRCLK.

•

The SDOUT(s) MSB (playback) data is transmitted at the same time as LRCLK edge and captured at the
next rising edge of SCLK.

•

If the LRCLK phase changes by more than 10 cycles of MCLK, the codec automatically resets.

SCLK

LRCLK = fS

MSB

LSB

… …

MSB

LSB

… …

SDIN

MSB

LSB

… …

MSB

LSB

… …

Left Channel

Right Channel

SDOUT

… …

Figure 2−1. MSB-First, Right-Justified, Serial-Interface Format

Summary of Contents for TAS3002

Page 1: ... 2001 Digital Audio Digital Speakers Data Manual SLAS307B ...

Page 2: ...8 kHz The 13 serial interface formats are listed and described in Section 2 1 The TAS3002 device uses a system clock generated by the internal phase locked loop PLL The reference clock for the PLL is provided by an external master clock MCLK of 256fS or 512fS or a 256fS crystal The TAS3002 device has six internally configurable general purpose input GPI terminals that control volume bass treble an...

Page 3: ...ts Sampling rates of 32 kHz 44 1 kHz or 48 kHz Master clock frequency of 256fS or 512fS Can have crystal input to replace MCLK Crystal input frequency is 256fS Six GPI terminals for volume bass treble up down control mute and selection of equalization filters 1 3 Functional Block Diagram Figure 1 1 is a block diagram showing the major functions of the TAS3002 ...

Page 4: ...o DAC CAP_PLL MCLK XTALO MCLKO CLKSEL SDIN2 SDIN1 SDATA Control LRCLK O SCLK O SDOUT1 L L R SDOUT2 32 Bit Audio Signal Processor AOUTL VCOM AOUTR L R R 32 Bit Audio Signal Processor OSC CLK Select PLL Reference Voltage Supplies Analog Supplies Digital IFM S RESET INPA ALLPASS XTALI AV SS REF V RFILT AV DD AV SS V REFM DV DD DV SS V REFP I 2 C SDOUT0 Figure 1 1 TAS3002 Block Diagram ...

Page 5: ...e 1 2 TAS3002 Terminal Assignments 1 5 Terminal Functions Table 1 1 lists the terminals in alphanumeric order by signal name along with the terminal number terminal type and a description of the terminal function Table 1 1 TAS3002 Terminal Functions TERMINAL I O DESCRIPTION NAME NO I O DESCRIPTION AINLM 46 I ADC left channel analog input antialias capacitor AINLP 47 I ADC left channel analog input...

Page 6: ...rcuit board routing channel PWR_DN 8 I Logic high places the TAS3002 device in power down mode RESET 6 I Logic low resets the TAS3002 device to the initial state RINA 40 I Right channel analog input 1 RINB 41 I Right channel analog input 2 SCL 15 I O I2C clock connection SCLK O 20 I O Shift bit clock input output when IFM S is high SDA 16 I O I2C data connection SDIN1 22 I Serial data input 1 SDIN...

Page 7: ...1 6 ...

Page 8: ...ges must be at least 3 ns apart If the LRCLK phase changes by more than 10 cycles ofMCLK the codec automatically resets The TAS3002 device is compatible with 13 different serial interfaces Available interface options are I2S right justified and left justified Table 2 1 indicates how the 13 options are selected using the I2C bus and the main control register MCR I2C address 01h All serial interface...

Page 9: ...owing characteristics of this protocol Left channel is transmitted when LRCLK is high The SDIN s recorded data is justified to the trailing edge of the LRCLK The SDOUT s MSB playback data is transmitted at the same time as LRCLK edge and captured at the next rising edge of SCLK If the LRCLK phase changes by more than 10 cycles ofMCLK the codec automatically resets SCLK LRCLK fS MSB LSB MSB LSB SDI...

Page 10: ...f this protocol Left channel is transmitted when LRCLK is low SDIN is sampled with the rising edge of SCLK SDOUT is transmitted on the falling edge of SCLK If the LRCLK phase changes by more than 10 cycles ofMCLK the codec automatically resets SCLK LRCLK fS X LSB SDIN X LSB Left Channel Right Channel SDOUT MSB MSB X LSB X LSB MSB MSB Figure 2 2 I2S Serial Interface Format ...

Page 11: ...ing characteristics of this protocol Left channel is transmitted when LRCLK is high The SDIN data is justified to the leading edge of the LRCLK The MSBs are transmitted at the same time as LRCLK edge and captured at the next rising edge of SCLK SCLK LRCLK fS MSB LSB MSB LSB SDIN MSB LSB MSB LSB Left Channel Right Channel SDOUT Figure 2 3 MSB Left Justified Serial Interface Format ...

Page 12: ...te 1 1 256fS 10 ns tsu SDIN SDIN setup before SCLK rising edge 20 ns th SDIN SDIN hold after SCLK rising edge 100 ns f LRCLK LRCLK frequency 32 44 1 48 kHz Duty cycle 50 NOTE 1 Maximum of 50 pF external load on SDOUT SCLK LRCLK SDIN1 SDIN2 SDOUT1 SDOUT2 SDOUT0 tc SCLK td SDOUT tsu SDIN th SDIN td SLR tf SCLK tr SCLK td SLR Figure 2 4 For Right Left Justified and I2S Serial Protocols ...

Page 13: ...2 6 ...

Page 14: ...ency response from 20 Hz to 20 kHz at a sampling frequency of 48 kHz without alias frequency problems AINRP AINRM AINLM AINLP 24 Bit Stereo ADC RINA RINB AINRM AINRP AINLM AINLP LINA LINB Reference Voltage 1200 pF 1200 pF 0 47 µF 0 47 µF 1 1 0 47 µF 0 47 µF 1 1 2 2 1 Analog Inputs Use 0 47 µF for 20 Hz Cutoff 2 Anti Alias Capacitors for fS 48 kHz Input Select Command From Internal Controller 3 Tie...

Page 15: ...ing an external amplifier The circuit shown in Figure 3 3 boosts the output level to 1 Vrms when it has a gain of 1 414 and provides improved signal to noise ratio SNR Since this circuit lowers the noise floor THD N is improved also AOUTR 10 µF Analog Output Adjust Capacitors for Desired Low Frequency Response 24 Bit DAC AOUTL VCOM 0 1 µF AGND 5 Op Amp 2 5 Op Amp 2 TLV2362 or Equilvalent TLV2362 o...

Page 16: ...Reference Voltage Filter Figure 3 4 shows the TAS3002 reference voltage filter 0 1 µF 15 µF 0 1 µF 1 µF 0 1 µF 4 2 3 45 44 VREFP AV SS AV SS REF V RFILT V REFM TAS3002 Figure 3 4 TAS3002 Reference Voltage Filter ...

Page 17: ...3 4 ...

Page 18: ...t of 0 infinity dB Soft mute can be enabled by either asserting the mute GPI terminal see Section 7 6 1 or sending a mute command over the I2C bus Subsequent assertions of the mute GPI terminal toggle soft mute off and on 4 3 Input Mixer Control The TAS3002 device is capable of mixing and multiplexing three channels SDIN1 SDIN2 and the ADC output of serial audio data The mixing is controlled throu...

Page 19: ... monaural channel This mixer has a fixed gain of 6 dB so that full scale inputs on L_sum and R_sum do not produce clipping on the resulting L R_sum The output of this mixer is present on terminal 24 SDOUT2 and is generally used for a digitally mixed subwoofer or center channel application 4 5 Treble Control The treble gain level may be adjusted within the range of 15 dB to 15 dB with 0 5 dB step r...

Page 20: ...lf filter with a corner frequency of 250 Hz at a 48 kHz sample rate The gain values for bass control can be found in Section NO TAG 4 7 De Emphasis Mode DM De emphasis is implemented in the DAC and is software controlled De emphasis is valid at 44 1 kHz and 48 kHz To enable de emphasis values are written into the analog control register via the I2C command See Section 4 8 for analog control regist...

Page 21: ...nalog Control Register Description BIT FIELD NAME TYPE DESCRIPTION 7 Reserved R W Reset to 0 6 Reserved R W Reset to 0 5 4 Reserved R W Reserved Bits 5 and 4 return 0s when read 3 2 DM 1 0 R W De emphasis control 00 De emphasis off initial condition after reset 01 48 kHz sample rate de emphasis selected 10 44 1 kHz sample rate de emphasis selected 11 Reserved 1 INP R W Analog input select 0 LINA a...

Page 22: ... 1 Loudness Biquads Loudness biquad filters for the left and right channels are independently programmable via I2C Their subaddresses are 21h and 22h respectively The digital filters are written as five 24 bit 4 20 hex coefficients for each channel 4 9 2 Loudness Gain Loudness gain values for the left and right channels are independently programmable via I2C Their subaddresses are 23h and 24h resp...

Page 23: ...ocessing Block Diagram The DRCE instruction consists of eight bytes that must be sent each time in the order shown in the example code of NO TAG Each instruction downloaded must be eight bytes If only one byte is changed all eight bytes must be transmitted The first two bytes remain the same for every instruction however the last six bytes can be programmed using hexadecimal values from the corres...

Page 24: ...Reserved R Reserved 1 0 W R W Serial port word length 00 16 bit 01 18 bit 10 20 bit 11 24 bit 4 13 Main Control Register 2 43h The TAS3002 device contains two main control registers main control register 1 MCR1 and main control register 2 MCR2 The MCR2 register contains the bits associated with the AllPass function and the download of bass and treble control information and it is accessed via I2C ...

Page 25: ...4 8 ...

Page 26: ... into analog waveforms by the DAC Alternatively filters can be loaded by asserting terminals on the GPI port 5 1 2 Biquad Structure The biquad structure that is used for the parametric equalization filters is as follows H z b0 b1z 1 b2z 2 a0 a1z 1 a2z 2 NOTE a0 is fixed at value 1 and is not downloadable The coefficients for these filters are represented in 4 20 format 4 bits for the integer part ...

Page 27: ...5 2 ...

Page 28: ... master or slave mode therefore at least one device connected to the I2C bus must operate in master mode 6 2 I2C Protocol The bus standard uses transitions on SDA while the clock is high to indicate start and stop conditions A high to low transition on SDA indicates a start and a low to high transition indicates a stop Normal data bit transitions must occur within the low time of the clock period ...

Page 29: ...her licensed I2C audio devices In addition to the 7 bit device address subaddresses direct communication to the proper memory location within the device A complete table of subaddresses and control registers is provided in Appendix A For example to change bass to 10 dB gain Section 6 3 1 shows the data that is written to the I2C port Table 6 2 I2C Address Byte Table I2C ADDRESS BYTE A6 A1 CS1 A0 R...

Page 30: ...he last byte read It is required to send an I2C Stop command after the last byte and not a Send Ack 2 The I2C Start and I2C Stop commands are the same for both I2C read and I2C write 6 3 3 I2C Wait States The TAS3002 device performs interpolation algorithms for its volume and tone controls If a volume or tone change is sent to the part via I2C the command sent after the volume or tone bass and tre...

Page 31: ...significant bit MSB of the TAS3002 subaddress must be set high and the subaddress also with MSB set high must be programmed into the SMBus command byte This operation signals the TAS3002 device that the next byte is the SMBus byte count byte The next byte after the byte count is then entered into the device as the first byte of data SMBus Command Byte 68h 8rh xx dd dd dd TAS3002 Address Subaddress...

Page 32: ...ecognize bus waiting or if the master times out on a long wait the master must not send consecutive I2C SMBus commands without a time interval of 200 ms between transactions 6 4 4 TAS3002 SMBus Readback The TAS3002 device supports a subset of SMBus readback When an SMBus read command is sent to the device LSB high it answers with the subaddress and the last six bytes written SMBus Command Byte Byt...

Page 33: ...6 6 ...

Page 34: ...the device Before reading the EEPROM the serial audio port defaults to I2S mode The TAS3002 device allows the user to update volume bass and treble dynamically by an I2C slave command or by a simple GPI input The GPI can select volume up and down bass treble up and down or digital equalizations Up to five different equalizations that is flat jazz rock voice etc can be stored in the external EEPROM...

Page 35: ...80 of VDD In the case where the system power supplies are slow in reaching their final voltage or where there is a difference in the time the system power supplies take to become stable the TAS3002 reset can be delayed by a simple RC circuit 0 1 µF DVDD 6 TAS3002 RESET 10 kΩ DVSS Figure 7 1 TAS3002 Reset Circuit The reset delay for the above circuit can be calculated by the simple equation trd 0 8...

Page 36: ... purged so that when reset initialization is complete only valid inputs are sent to the system output 7 3 Power Down Mode The TAS3002 device has an asynchronous power down mode In the power down mode the internal control registers and equalization programming of the device are stored in the device To enter power down mode 1 Assert the power down control signal 1 2 Set the serial audio input clocks...

Page 37: ...ied low in normal operation This function is reserved for factory test and must not be asserted 7 5 Internal Interface Figure 7 3 shows the flow chart of the interface between the microcontroller and its peripheral blocks 7 6 GPI Terminal Programming During initialization the microcontroller fetches a control byte from its EEPROM or receives a command from I2C 7 6 1 GPI Interface The six GPI termi...

Page 38: ... second changes the function of the GPI terminals to control mute and equalization To return to volume bass and treble control simultaneously set GPI terminals 2 and 3 low for 1 second When a GPI terminal is activated the TAS3002 device echoes its function over I2C to a TAS3001 device mapped to address 6Ah Therefore a system with two audio equalization chips can be implemented without the need for...

Page 39: ...ume and MCR Slave Write Initialize TAS3002 TAS3001 GPI Power Down Load Parameters and Coefficients to DSP Volume Bass Treble Up Down Echo to TAS3001 Switch BQ Set Save Volume Mute Save PWR_DN Stop PLL Stop DRC_OFF DRC Figure 7 3 Internal Interface Flow Chart ...

Page 40: ... 040h 04Eh 15 Biquad 1 04Fh 05Dh 15 Biquad 2 05Eh 06Ch 15 Biquad 3 Left channel 06Dh 07Bh 15 Biquad 4 Left channel 07Ch 08Ah 15 Biquad 5 08Bh 099h 15 Biquad 6 09Ah 1 0 dB bass 09Bh 1 0 dB treble 09Ch 0A1h 6 Bass break 0A2h 0A7h 6 Treble break 0A8h 110h 105 Bass delta 111h 179h 105 Treble delta 17Ah 17Fh 6 Bass set point 180h 185h 6 Treble set point 186h 194h 15 Biquad 0 195h 1A3h 15 Biquad 1 1A4h ...

Page 41: ...eble 09Ch 0A1h 6 Bass break 0A2h 0A7h 6 Treble break 0A8h 110h 105 Bass delta 111h 179h 105 Treble delta 17Ah 17Fh 6 Bass set point 180h 185h 6 Treble set point 186h 194h 15 Biquad 0 195h 1A3h 15 Biquad 1 1A4h 1B2h 15 Biquad 2 TAS3001 1B3h 1C1h 15 Biquad 3 TAS3001 right and left channel 1C2h 1D0h 15 Biquad 4 right and left channel 1D1h 1DFh 15 Biquad 5 1E0h 1EEh 15 Biquad 6 TAS3001 1EFh 1 MCR 1F0h...

Page 42: ... 5DEh 5ECh 23Ch 24Ah 15 Biquad 4 Set 1 449h 457h 5EDh 5FBh 24Bh 259h 15 Biquad 5 458h 466h 5FCh 60Ah 25Ah 268h 15 Biquad 6 467h 475h 60Bh 619h 269h 277h 15 Biquad 0 476h 484h 61Ah 628h 278h 286h 15 Biquad 1 485h 493h 629h 637h 287h 295h 15 Biquad 2 494h 4A2h 638h 646h 296h 2A4h 15 Biquad 3 Set 2 4A3h 4B1h 647h 655h 2A5h 2B3h 15 Biquad 4 Set 2 4B2h 4C0h 656h 664h 2B4h 2C2h 15 Biquad 5 4C1h 4CFh 665...

Page 43: ... 5ECh 43Ah 448h 23Ch 24Ah 15 Biquad 4 Set 1 5EDh 5FBh 449h 457h 24Bh 259h 15 Biquad 5 5FCh 60Ah 458h 466h 25Ah 268h 15 Biquad 6 60Bh 619h 467h 475h 269h 277h 15 Biquad 0 61Ah 628h 476h 484h 278h 286h 15 Biquad 1 629h 637h 485h 493h 287h 295h 15 Biquad 2 638h 646h 494h 4A2h 296h 2A4h 15 Biquad 3 Set 2 647h 655h 4A3h 4B1h 2A5h 2B3h 15 Biquad 4 Set 2 656h 664h 4B2h 4C0h 2B4h 2C2h 15 Biquad 5 665h 673...

Page 44: ...rated conditions for extended periods may affect device reliability NOTE 1 Human body model per Method 3015 2 of MIL STD 833B 8 2 Recommended Operating Conditions TA 25 C AVDD 3 3 V DVDD 3 3 V Voltages at analog inputs and outputs and at AVDD are with respect to ground MIN NOM MAX UNIT Supply voltage AVDD 3 0 3 3 3 6 V Supply voltage DVDD 3 0 3 3 3 6 V Supply current analog Operating 34 mA Supply ...

Page 45: ...and 0 0 20 0 kHz ADC decimation filter LPF Pass band ripple 0 01 dB Stop band 24 1 kHz Stop band attenuation 80 dB Group delay 720 µs ADC high pass filter HPF Pass band 3 dB 0 87 Hz ADC high pass filter HPF Deviation from linear phase 20 Hz to 20 kHz 1 23 degrees 150 200 Amplitude dB 50 0 50 100 f Frequency Hz 0 2 fs 4 fs 6 fs 8 fs 10 fs 12 fs Figure 8 1 ADC Digital Filter Characteristics 60 100 A...

Page 46: ... kHz 20 bit I2S mode All terms characterized by frequency are scaled with the chosen sampling frequency fS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SNR EIAJ A weighted 93 dB Dynamic range 60 dB 1 kHz 88 dB Signal to noise distortion ratio 1 dB 1 kHz 20 Hz to 20 kHz 82 dB Power supply rejection ratio 1 kHz see Note 3 50 dB Idle channel tone rejection 110 dB Intermodulation distortion 80 dB ADC cr...

Page 47: ...ampling frequency fS See Figure 8 5 and Figure 8 6 for performance curves of the DAC digital filter PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Pass band 0 0 20 0 kHz Pass band ripple 0 005 dB Stop band 24 1 kHz Stop band attenuation 28 8 kHz to 3 MHz 75 dB Group delay 700 µs 60 100 Amplitude dB 40 20 f Frequency Hz 0 80 R 0 fs 2 1 fs 2 fs 3 fs 4 fs 5 fs Figure 8 5 DAC Filter Overall Frequency Char...

Page 48: ...se 0 5 0 5 dB Deviation from linear phase 1 4 degree DAC crosstalk 96 dB Jitter tolerance 150 ps Full scale single ended output voltage range 1 9 VPP DC offset 7 0 7 0 mV 8 9 DAC Output Performance Data TA 25 C AVDD 3 3 V DVDD 3 3 V The output load resistance is connected through a dc blocking capacitor PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output load resistance 10 kΩ Output load capacitance...

Page 49: ...r Rise time for SDA and SCL 1000 ns tf Fall time for SDA and SCL 300 ns tsu sto Setup time for stop condition 4 0 µs C b Capacitive load for each bus line 400 pF NOTE 6 A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL SDA P S Valid Change of Data Allowed P SCL t buf th sta tr th dat tf th sta tsu dat tsu st...

Page 50: ...ereo and 2 1 channel applications respectively TAS3002 Master RESET Analog In 3 3 VDD Analog Out SPDIF or USB I2S EEPROM I2C Clock Select Logic B T V EQ Switches NOTE Items such as the PLL network and power supplies are omitted for clarity Figure 9 1 Stereo Application ...

Page 51: ...log Out To Satellite Amplifiers SPDIF or USB I2S EEPROM I2C Clock Select Logic B T V EQ Sub Vol I2C TAS3001 Address 6Ah I2S_OUT Slave Analog Out SDOUT2 I2S PCM1744 NOTE Items such as the PLL network and power supplies are omitted for clarity Figure 9 2 TAS3002 Device 2 1 Channels ...

Page 52: ...PFB package PFB S PQFP G48 PLASTIC QUAD FLATPACK 4073176 B 10 96 Gage Plane 0 13 NOM 0 25 0 45 0 75 Seating Plane 0 05 MIN 0 17 0 27 24 25 13 12 SQ 36 37 7 20 6 80 48 1 5 50 TYP SQ 8 80 9 20 1 05 0 95 1 20 MAX 0 08 0 50 M 0 08 0 ā7 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Falls within JEDEC MS 026 ...

Page 53: ... temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS no Sb Br TI defines Gr...

Page 54: ...PACKAGE OPTION ADDENDUM www ti com 3 Apr 2013 Addendum Page 2 ...

Page 55: ...evice Package Type Package Drawing Pins SPQ Reel Diameter mm Reel Width W1 mm A0 mm B0 mm K0 mm P1 mm W mm Pin1 Quadrant TAS3002PFBR TQFP PFB 48 0 330 0 16 4 9 6 9 6 1 5 12 0 16 0 Q2 PACKAGE MATERIALS INFORMATION www ti com 5 Nov 2012 Pack Materials Page 1 ...

Page 56: ...ensions are nominal Device Package Type Package Drawing Pins SPQ Length mm Width mm Height mm TAS3002PFBR TQFP PFB 48 0 367 0 367 0 38 0 PACKAGE MATERIALS INFORMATION www ti com 5 Nov 2012 Pack Materials Page 2 ...

Page 57: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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