Texas Instruments TAS3002, Data Manual

Page: 49 / 57

8−6
8.10 I
2
C Serial Port Timing Characteristics
MIN MAX UNIT
f(SCL) SCL clock frequency 0 100 kHz
t(buf) Bus free time between start and stop 4.7
µ
s
t(low) Low period of SCL clock 4.7
µ
s
t(high) High period of SCL clock 4.0
µ
s
th(sta) Hold time repeated start 4.0
µ
s
tsu(sta) Setup time repeated start 4.7 20
µ
s
th(dat) Data hold time (See Note 6) 0
µ
s
tsu(dat) Data setup time 250 ns
tr Rise time for SDA and SCL 1000 ns
tf Fall time for SDA and SCL 300 ns
tsu(sto) Setup time for stop condition 4.0
µ
s
C(b) Capacitive load for each bus line 400 pF
NOTE 6: A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of
SCL.
SDA
P S
Valid
Change
of Data
Allowed
P
SCL
t(buf)
th(sta)
tr
th(dat)
tf
th(sta)
tsu(dat)
tsu(sta)
tsu(sto)
Data
Line
Stable
NOTE: t(low) is measured from the end of tf to the beginning of tr.
t(high) is measured from the end of tr to the beginning of tf.
Figure 8−7. I
2
C Bus Timing