Texas Instruments TAS2770YFF, User Manual

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Digital Audio Interfaces
7 SLOU500 – December 2017
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Copyright © 2017, Texas Instruments Incorporated
TAS2770YFF Evaluation Module
8 Digital Audio Interfaces
The various digital audio interfaces on the TAS2770YFF Reference Board can be selected through
hardware settings and software settings. Several headers close to the TAS2770YFF device allow access
to the following digital audio signals:
• I2S data out (SDOUT) from the TAS2770YFF (for example, current and voltage sense data)
• I2S data in (SDIN) to the TAS2770YFF
• I2S word clock or frame sync (FSYNC)
• I2S bit clock (SBCLK)
• PDM clock (PDMCLK0) – optional input source for TAS2770YFF
• PDM clock (PDMCLK1) – optional input source for TAS2770YFF
• PDM data (PDMD0) – optional input source for TAS2770YFF
• PDM data (PDMD1) – optional input source for TAS2770YFF
• I
2
C clock (SCLK)
• I
2
C data (SDA)
The TAS2770YFF device can be configured for Soundwire
SM
mode as well:
• Soundwire
SM
clock: SBCLK
• Soundwire
SM
data: SDOUT
• Soundwire
SM
address: SDA
• Soundwire
SM
address: FSYNC
• Soundwire
SM
address: SCL
A jumper inserted in the SW slot of J13 sets the TAS2770YFF to Soundwire
SM
mode. Also, J12 should be
removed to enable use of J11 to set the desired device address in this mode.
The selection between USB (internal) and external inputs is controlled by jumpers J2 and J6. These
jumpers set TDM and I
2
C, respectively.