Contents
Preface
...............................................................................................................................
7
1
Introduction
................................................................................................................
8
1.1
Purpose of the Peripheral
.......................................................................................
8
1.2
Features
...........................................................................................................
8
1.3
Functional Block Diagram
.......................................................................................
9
1.4
Industry Standard(s) Compliance Statement
.................................................................
9
2
Peripheral Architecture
..............................................................................................
10
2.1
Clock Control
....................................................................................................
10
2.2
Signal Descriptions
.............................................................................................
11
2.3
Pin Multiplexing
.................................................................................................
11
2.4
Protocol Description
............................................................................................
11
2.5
VLYNQ Functional Description
...............................................................................
12
2.6
Initialization
......................................................................................................
15
2.7
Auto-Negotiation
................................................................................................
15
2.8
Address Translation
............................................................................................
16
2.9
Flow Control
.....................................................................................................
19
2.10
Reset Considerations
..........................................................................................
20
2.11
Interrupt Support
................................................................................................
20
2.12
EDMA Event Support
..........................................................................................
22
2.13
Power Management
............................................................................................
23
2.14
Endianness Considerations
...................................................................................
23
2.15
Emulation Considerations
.....................................................................................
23
3
VLYNQ Port Registers
................................................................................................
24
3.1
Revision Register (REVID)
....................................................................................
25
3.2
Control Register (CTRL)
.......................................................................................
26
3.3
Status Register (STAT)
........................................................................................
28
3.4
Interrupt Priority Vector Status/Clear Register (INTPRI)
..................................................
30
3.5
Interrupt Status/Clear Register (INTSTATCLR)
............................................................
30
3.6
Interrupt Pending/Set Register (INTPENDSET)
............................................................
31
3.7
Interrupt Pointer Register (INTPTR)
.........................................................................
31
3.8
Transmit Address Map Register (XAM)
......................................................................
32
3.9
Receive Address Map Size 1 Register (RAMS1)
..........................................................
33
3.10
Receive Address Map Offset 1 Register (RAMO1)
........................................................
33
3.11
Receive Address Map Size 2 Register (RAMS2)
..........................................................
34
3.12
Receive Address Map Offset 2 Register (RAMO2)
........................................................
34
3.13
Receive Address Map Size 3 Register (RAMS3)
..........................................................
35
3.14
Receive Address Map Offset 3 Register (RAMO3)
........................................................
35
3.15
Receive Address Map Size 4 Register (RAMS4)
..........................................................
36
3.16
Receive Address Map Offset 4 Register (RAMO4)
........................................................
36
3.17
Chip Version Register (CHIPVER)
...........................................................................
37
3.18
Auto Negotiation Register (AUTNGO)
.......................................................................
37
4
Remote Configuration Registers
.................................................................................
38
Appendix A VLYNQ Protocol Specifications
........................................................................
39
A.1
Introduction
......................................................................................................
39
SPRU938B – September 2007
Table of Contents
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