Texas Instruments RM48 series, Technical Reference Manual

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System and Peripheral Control Registers
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170 SPNU503C – March 2018
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Architecture
2.5.1.48 System Exception Status Register (SYSESR)
The SYSESR register, shown in Figure 2-53 and described in Table 2-67 , shows the source for different
resets encountered. Previous reset source status bits are not automatically cleared if new resets occur.
After reading this register, the software should clear any flags that are set so that the source of future
resets can be determined. Any bit in this register can be cleared by writing a 1 to the bit.
Figure 2-53. System Exception Status Register (SYSESR) [offset = E4h]
31 16
Reserved
R-0
15 14 13 12 8
PORST OSCRST WDRST Reserved
R/WC-X R/WC-X* R/WC-X* R-0
7 6 5 4 3 2 0
Reserved CPURST SWRST EXTRST Reserved
R-0 R/WC-X* R/WC-X* R/WC-X* R-0
LEGEND: R/W = Read/Write; R = Read only; C= Clear; X = value unchanged after reset; X* = 0 after PORST but unchanged after other
resets; -n = value after reset
Table 2-67. System Exception Status Register (SYSESR) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reads return 0. Writes have no effect.
15 PORST Power-on reset. This bit is set when a power-on reset occurs, either internally asserted by the VMON or
externally asserted by the nPORRST pin.
0 No power-on reset has occurred since this bit was last cleared.
1 A reset was caused by a power-on reset. (This bit should be cleared after being read so that
subsequent resets can be properly identified as not being power-on resets.)
14 OSCRST Reset caused by an oscillator failure or PLL cycle slip. This bit is set when a reset is caused by an
oscillator failure or PLL slip.
Note: The action taken when an oscillator failure or PLL slip is detected must configured in the
PLLCTL1 register.
0 No reset has occurred due to an oscillator failure or a PLL cycle slip.
1 A reset was caused by an oscillator failure or a PLL cycle slip.
13 WDRST Watchdog reset flag. This bit is set when the last reset was caused by the digital windowed watchdog.
During debugging, the ICEPICK logic implemented on the microcontroller also allows a system reset to
be generated via the debug logic (DBGRST). This DBGRST reset is also indicated on the WDRST bit of
the SYSESR. This flag can also be set via a reset driven by ICEPICK.
0 No reset has occurred because of the DWWD.
1 A reset was caused by the DWWD.
12-6 Reserved 0 Reads return 0. Writes have no effect.
5 CPURST CPU reset flag. This bit is set when the CPU is reset.
Note: A CPU reset can be initiated by the CPU self-test controller (LBIST) or by changing the
memory protection (MMU/MPU) configuration in CPURSTCR register.
0 No CPU reset has occurred.
1 A CPU reset occurred.
4 SWRST Software reset flag. This bit is set when a software system reset has occurred.
Note: A software system reset can be initiated by writing to the RESET bits in the SYSECR
register.
0 No software reset has occurred.
1 A software reset occurred.