Message Handling
1064
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Controller Area Network (DCAN) Module
23.8.3 Transmission of Messages in Event Driven CAN Communication
If the shift register of the CAN Core is ready for loading and if there is no data transfer between the IFx
Registers and Message RAM, the d bits in the Message Valid Register and the TxRqst bits in the
Transmission Request Register are evaluated. The valid message object with the highest priority pending
transmission request is loaded into the shift register by the Message Handler and the transmission is
started. The message object’s NewDat bit is reset.
After a successful transmission and if no new data was written to the message object (NewDat = 0) since
the start of the transmission, the TxRqst bit will be reset. If TxIE is set, IntPnd will be set after a successful
transmission. If the DCAN has lost the arbitration or if an error occurred during the transmission, the
message will be retransmitted as soon as the CAN bus is free again. If meanwhile the transmission of a
message with higher priority has been requested, the messages will be transmitted in the order of their
priority.
If Automatic Retransmission mode is disabled by setting the DAR bit in the CAN Control Register
,
the
behavior of bits TxRqst and NewDat in the Message Control Register of the Interface Register set is as
follows:
•
When a transmission starts, the TxRqst bit of the respective Interface Register set is reset, while bit
NewDat remains set.
•
When the transmission has been successfully completed, the NewDat bit is reset.
When a transmission failed (lost arbitration or error) bit NewDat remains set. To restart the transmission,
the application has to set TxRqst again.
Received Remote Frames do not require a Receive Object. They will automatically trigger the
transmission of a Data Frame, if in the matching Transmit Object the RmtEn bit is set.
23.8.4 Updating a Transmit Object
The CPU may update the data bytes of a Transmit Object any time via the IF1/IF2 Interface Registers,
neither d nor TxRqst have to be reset before the update.
Even if only a part of the data bytes are to be updated, all four bytes in the corresponding IF1/IF2 Data A
Register or IF1/IF2 Data B Register have to be valid before the content of that register is transferred to the
message object. Either the CPU has to write all four bytes into the IF1/IF2 Data Register or the message
object is transferred to the IF1/IF2 Data Register before the CPU writes the new data bytes.
When only the data bytes are updated, first 0x87 can be written to bits [23:16] of the Command Register
and then the number of the message object is written to bits [7:0] of the Command Register, concurrently
updating the data bytes and setting TxRqst with NewDat.
To prevent the reset of TxRqst at the end of a transmission that may already be in progress while the data
is updated, NewDat has to be set together with TxRqst in event driven CAN communication. For details,
see
When NewDat is set together with TxRqst, NewDat will be reset as soon as the new transmission has
started.
23.8.5 Changing a Transmit Object
If the number of implemented message objects is not sufficient to be used as permanent message objects
only, the Transmit Objects may be managed dynamically. The CPU can write the whole message
(Arbitration, Control, and Data) into the Interface Register. The bits [23:16] of the Command Register can
be set to 0xB7 for the transfer of the whole message object content into the message object. Before
changing the configuration of a message object, MsgVal has to be reset (see
If a previously requested transmission of this message object is not completed but already in progress, it
will be continued; however it will not be repeated if it is disturbed.
To only update the data bytes of a message to be transmitted, bits [23:16] of the Command Register
should be set to 0x87.
