Texas Instruments PanelBus TFP503, Manual

Page: 9 / 27

PanelBus 
SLDS149 − AUGUST 2004
9
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
ac specifications (continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
1 pixel/clock
PIXS = Low ST = Low
CL = 10 pF
1.9
ns
OCK_INV = High
ST = High
CL = 10 pF
1.9
ns
tsu(2)
Setup time, data, and control signals to
2 pixel/clock
PIXS = High ST = Low
CL = 10 pF
2.9
ns tsu(2)
Setup time, data, and control signals to
rising edge of ODCK (see Note 11)
STAG = High
OCK_INV = High ST = High
CL = 10 pF
2.9
ns
2 pixel & STAG
PIXS = High ST = Low
CL = 10 pF
2.0
ns
STAG = Low
OCK_INV = High ST = High
CL = 10 pF
2.0
ns
1 pixel/clock
PIXS = Low ST = Low
CL = 10 pF
0.5
ns
th(2)
Hold time, data, and control signals to
OCK_INV = High
ST = High
CL = 10 pF
0.5
ns
th(2)
Hold time, data, and control signals to
rising edge of ODCK (see Note 11)
2 pixel & STAG
PIXS = High ST = Low
CL = 10 pF
1.4
ns
STAG = Low
OCK_INV = High ST = High
CL = 10 pF
1.4
ns
f(ODCK) ODCK frequency
PIXS = Low 25 165
MHz f(ODCK) ODCK frequency
PIXS = High 12.5 82.5
MHz
ODCK duty cycle 40% 50% 60%
td(PDL) Delay from PD low to Hi-Z outputs 18 ns
td(PDOL) Delay from PDO low to Hi-Z outputs 18 ns
t(HSC)
Time between DE transitions to SCDT low
(see Note 13)
165 MHz 25 ms
tt(FSC)
Time from DE low to SCDT high
(see Note 13)
8 trans(DE)†
td(st)
ODCK latching edge to QE[23:0] data
output STAG = Low
PIXS = High 0.5
t(pixel)
ns
† trans(DE) is one transition (low-to-high or high-to-low) of the DE signal.
NOTES: 11. Data and control signals are: QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[2:1].
13. Link active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity.