PanelBus
SLDS149 − AUGUST 2004
10
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
timing diagrams
80%
20%
80%
20%
tr(2)
tf(2)
ODCK
80%
80%
20%
20%
tr(1)
tf(1)
QE[23:0], QO[23:0], DE,
CTL[2:1], HSYNC, VSYNC
Figure 1. Rise and Fall Time of ODCK
Figure 2. Rise and Fall Time of Data and Control Signals
f(ODCK)
ODCK
Figure 3. ODCK Frequency
tsu(1)
th(1)
tsu(2)
th(2)
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
ODCK
QE[23:0], QO[23:0], DE,
CTL[2:1], HSYNC, VSYNC
OCK_INV
Figure 4. Data Setup and Hold Time to Rising and Falling Edge of ODCK
Figure 5. ODCK High to QE[23:0] Staggered
Data Output
Figure 6. Analog Input Intra-Pair
Differential Skew
50%
VOH
td(st)
ODCK
QE[23:0]
50%
tsk(D)
Tx+
Tx-
Figure 7. Delay From PD Low to Hi-Z Outputs
Figure 8. Delay From PDO Low to Hi-Z Outputs
PD
QE[23:0], QO[23:0],
ODCK, DE, CTL[2:1],
HSYNC, VSYNC, SCDT
td(PDL)
VIL
PDO
QE[23:0], QO[23:0],
ODCK, DE, CTL[2:1],
HSYNC, VSYNC
td(PDOL)
VIL
