Texas Instruments PanelBus TFP503, Manual

Page: 8 / 27

PanelBus 
SLDS149 − AUGUST 2004
8
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
ac specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VID(2) Differential input sensitivity (see Note 8) 150 mVp−p
VID(3) Maximum differential input 1560 mVp−p
tsk(D)
Analog input intra-pair (+ to −) differential
skew (see Note 12) 0.4
t(bit)†
ns
tsk(CC)
Analog input inter-pair or channel-to-channel
skew (see Note 12) 1.0
t(pixel)‡
ns
Worst case differential input clock jitter
tolerance (see Notes 9 and 12)
112 MHz, 1 pixel/clock 200 ps
tr(1)
Rise time of data and control signals
ST = Low, CL = 10 pF 1.9
ns tr(1)
Rise time of data and control signals
(see Notes 10 and 11)
ST = High, CL = 10 pF 1.9
ns
tf(1)
Fall time of data and control signals
ST = Low, CL = 10 pF 1.9
ns tf(1)
Fall time of data and control signals
(see Notes 10 and 11)
ST = High, CL = 10 pF 1.9
ns
tr(2) Rise time of ODCK clock (see Note 10)
ST = Low, CL = 10 pF 1.9
ns tr(2) Rise time of ODCK clock (see Note 10)
ST = High, CL = 10 pF 1.9
ns
tf(2) Fall time of ODCK clock (see Note 10)
ST = Low, CL = 10 pF 1.9
ns tf(2) Fall time of ODCK clock (see Note 10)
ST = High, CL = 10 pF 1.9
ns
1 pixel/clock
PIXS = Low ST = Low
CL = 10 pF
1.2
ns
OCK_INV = Low
ST = High
CL = 10 pF
1.2
ns
tsu(1)
Setup time, data, and control signals to falling
2 pixel/clock
PIXS = High ST = Low
CL = 10 pF
2.7
ns tsu(1)
Setup time, data, and control signals to falling
edge of ODCK (see Note 11)
STAG = High
OCK_INV = Low ST = High
CL = 10 pF
2.7
ns
2 pixel & STAG
PIXS = High ST = Low
CL = 10 pF
1.7
ns
STAG = Low
OCK_INV = Low ST = High
CL = 10 pF
1.7
ns
1 pixel/clock
PIXS = Low ST = Low
CL = 10 pF
0.9
ns
th(1)
Hold time, data, and control signals to falling
OCK_INV = Low
ST = High
CL = 10 pF
0.9
ns
th(1)
Hold time, data, and control signals to falling
edge of ODCK (see Note 11)
2 pixel and STAG
PIXS = High ST = Low
CL = 10 pF
2.9
ns
STAG = Low
OCK_INV = Low ST = High
CL = 10 pF
2.9
ns
† t(bit) is 1/10 the pixel time, t(pixel)
‡ t(pixel) is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to t(pixel) in 1-pixel/clock mode or 2 t(pixel) when
in 2-pixel/clock mode.
NOTES: 8. Specified as ac parameter to include sensitivity to overshoot, undershoot, and reflection.
9. Measured differentially at 50% crossing using ODCK output clock as trigger.
10. Rise and fall times measured as time between 20% and 80% of signal amplitude.
11. Data and control signals are: QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[2:1].
12. By characterization
13. Link active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity.