Texas Instruments OMAP36 Series, Technical Reference Manual

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IVA2.2 Subsystem Register Manual
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Bits Field Name Description Type Reset
12 AID2 Allowed ID 2: RW 1
AID2 = 0: VBus requests with PrivID == 2 are notallowed regardless
of permission settings (UW, UR, SW, SR).
AID2 = 1: VBus requests with PrivID == 2 are permitted if access
type is allowed as defined by permission settings (UW, UR, SW,
SR).
11 AID1 Allowed ID 1: RW 1
AID1 = 0: VBus requests with PrivID == 1 are notallowed regardless
of permission settings (UW, UR, SW, SR).
AID1 = 1: VBus requests with PrivID == 1 are permitted if access
type is allowed as defined by permission settings (UW, UR, SW,
SR).
10 AID0 Allowed ID 0: RW 1
AID0 = 0: VBus requests with PrivID == 0 are notallowed regardless
of permission settings (UW, UR, SW, SR).
AID0 = 1: VBus requests with PrivID == 0 are permitted if access
type is allowed as defined by permission settings (UW, UR, SW,
SR).
9 EXT External Allowed ID: RW 1
AIDm = 0: VBus requests with PrivID >= 6 are notallowed regardless
of permission settings (UW, UR, SW, SR).
AIDm = 1: VBus requests with PrivID >= 6 are permitted if access
type is allowed as defined by permission settings (UW, UR, SW,
SR).
8:6 Reserved Write reset value for future compatibility. Read returns reset value. RW 0x3
5 SR Supervisor Read permission: RW 1
SR = 0: Supervisor read accesses are not allowed
SR = 1: Supervisor write accesses are allowed
4 SW Supervisor Write permission: RW 1
SW = 0: Supervisor write accesses are not allowed
SW = 1: Supervisor write accesses are allowed
3 SX Supervisor Execute permission: RW 0
SX = 0: Supervisor execute accesses are not allowed
SX = 1: Supervisor execute accesses are allowed
2 UR User Read permission: RW 1
UR = 0: User read accesses are not allowed
UR = 1: User write accesses are allowed
1 UW User Write permission: RW 1
UW = 0: User write accesses are not allowed
UW = 1: User write accesses are allowed
0 UX User Execute permission: RW 0
UX = 0: User execute accesses are not allowed
UX = 1: User execute accesses are allowed
Table 5-261. Register Call Summary for Register TPCC_MPPAj
IVA2.2 Subsystem Basic Programming Model
• Internal Memory : [0] [1] [2] [3] [4]
IVA2.2 Subsystem Register Manual
• TPCC Register Mapping Summary : [5]
892 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated