Texas Instruments OMAP36 Series, Technical Reference Manual

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IVA2.2 Subsystem Register Manual
Table 5-234. TPCC_DRAEj
Address Offset (0x8*j)
Physical address 0x01C0 0340 + (0x8*j) Instance IVA2.2 TPCC
Description DMA Region Access enable for bit N in Region i:
En = 0: Accesses through Region i address space to Bit N in any DMA Channel Register are not allowed.
Reads will return b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not
contribute to the generation of the TPCC region i interrupt.
En = 1: Accesses through Region i address space to Bit N in any DMA Channel Register are allowed. Reads
will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do
contribute to the generation of the TPCC region i interrupt.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16 E15 E14 E13 E12 E11 E10
Bits Field Name Description Type Reset
31 E31 DMA Region Access enable for Region i, bit #31 RW 0
30 E30 DMA Region Access enable for Region i, bit #30 RW 0
29 E29 DMA Region Access enable for Region i, bit #29 RW 0
28 E28 DMA Region Access enable for Region i, bit #28 RW 0
27 E27 DMA Region Access enable for Region i, bit #27 RW 0
26 E26 DMA Region Access enable for Region i, bit #26 RW 0
25 E25 DMA Region Access enable for Region i, bit #25 RW 0
24 E24 DMA Region Access enable for Region i, bit #24 RW 0
23 E23 DMA Region Access enable for Region i, bit #23 RW 0
22 E22 DMA Region Access enable for Region i, bit #22 RW 0
21 E21 DMA Region Access enable for Region i, bit #21 RW 0
20 E20 DMA Region Access enable for Region i, bit #20 RW 0
19 E19 DMA Region Access enable for Region i, bit #19 RW 0
18 E18 DMA Region Access enable for Region i, bit #18 RW 0
17 E17 DMA Region Access enable for Region i, bit #17 RW 0
16 E16 DMA Region Access enable for Region i, bit #16 RW 0
15 E15 DMA Region Access enable for Region i, bit #15 RW 0
14 E14 DMA Region Access enable for Region i, bit #14 RW 0
13 E13 DMA Region Access enable for Region i, bit #13 RW 0
12 E12 DMA Region Access enable for Region i, bit #12 RW 0
11 E11 DMA Region Access enable for Region i, bit #11 RW 0
10 E10 DMA Region Access enable for Region i, bit #10 RW 0
9 E9 DMA Region Access enable for Region i, bit #9 RW 0
8 E8 DMA Region Access enable for Region i, bit #8 RW 0
7 E7 DMA Region Access enable for Region i, bit #7 RW 0
6 E6 DMA Region Access enable for Region i, bit #6 RW 0
5 E5 DMA Region Access enable for Region i, bit #5 RW 0
4 E4 DMA Region Access enable for Region i, bit #4 RW 0
3 E3 DMA Region Access enable for Region i, bit #3 RW 0
2 E2 DMA Region Access enable for Region i, bit #2 RW 0
1 E1 DMA Region Access enable for Region i, bit #1 RW 0
0 E0 DMA Region Access enable for Region i, bit #0 RW 0
881 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
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