Public Version
IVA2.2 Subsystem Register Manual
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Bits
Field Name
Description
Type
Reset
31:17
Reserved
Write 0s for future compatibility.
W
0x0000
16
TCERR
Clear Error for CCERR.TCERR:
W
0
Write of 1 clears the value of CCERR bit N.
Writes of 0 have no effect.
15:2
Reserved
Write 0s for future compatibility.
W
0x00
1
QTHRXCD1
Clear error for CCERR.QTHRXCD1:
W
0
Write of 1 clears the values of QSTAT1.WM, QSTAT1.THRXCD,
CCERR.QTHRXCD1
Writes of 0 have no effect.
0
QTHRXCD0
Clear error for CCERR.QTHRXCD0:
W
0
Write of 1 clears the values of QSTAT0.WM, QSTAT0.THRXCD,
CCERR.QTHRXCD0
Writes of 0 have no effect.
Table 5-231. Register Call Summary for Register TPCC_CCERRCLR
IVA2.2 Subsystem Register Manual
•
Table 5-232. TPCC_EEVAL
Address Offset
0x0320
Physical address
0x01C0 0320
Instance
IVA2.2 TPCC
Description
Error Eval Register
Type
W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
SET
EVAL
Bits
Field Name
Description
Type
Reset
31:2
Reserved
Write 0s for future compatibility.
W
0x00000000
1
SET
Error Interrupt Set:
W
0
CPU write of 1 to the SET bit causes the TPCC error interrupt to be
pulsed regardless of state of EMR/EMRH, QEMR, or CCERR.
CPU write of 0 has no effect.
0
EVAL
Error Interrupt Evaluate:
W
0
CPU write of 1 to the EVAL bit causes the TPCC error interrupt to be
pulsed if any errors have not been cleared in the EMR/EMRH,
QEMR, or CCERR registers.
CPU write of 0 has no effect.
Table 5-233. Register Call Summary for Register TPCC_EEVAL
IVA2.2 Subsystem Basic Programming Model
•
Error Reporting for EDMA Module
IVA2.2 Subsystem Register Manual
•
880
IVA2.2 Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated