Public Version
PRCM Basic Programming Model
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PRM internal event (event generator, sleep transition, wake-up transition, voltage processors, voltage
controller)
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Peripheral wake-up event for a peripheral with interrupt capability (GPTIMER[1..11], GPIO[1..6],
McBSP[1..5], UART[1..4], HS USB OTG, I2C[1..3], McSPI[1..4], MMC[1,2], SR[1,2])
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Module/device-level event not associated with any interrupt (DPLL recalibration, I/O wakeup)
The PRM interrupt is enabled by programming the PRM_IRQENABLE_<processor_name> register; the
interrupt status can be read from the PRM_IRQSTATUS_<processor_name> register.
The device has four processor interrupt registers:
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3.6.1.3.1 MPU Interrupt Event Sources
The MPU interrupt registers correspond to the interrupt sources connected to the interrupt line mapped to
the MPU interrupt controller.
Multiple events can activate this interrupt line:
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MPU peripheral group wake-up event
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Event-generator module end-of-on time and end-of-off time events
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Sleep or wake-up transition (SGX, USBHOST, IVA2, PER, DSS, CAM, NEON, EMU power domains)
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DPLL1/DPLL2/DPLL3/DPLL4/DPLL5 recalibration request
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I/O pad wake-up event
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Voltage processor 1 or 2 OPP Change Done event
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Voltage processor 1 or 2 new voltage reached the minimum voltage value allowed.
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Voltage processor 1 or 2 new voltage reached the maximum voltage value allowed.
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Voltage processor 1 or 2 time-out occurred while waiting for the power IC device acknowledge.
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Voltage processor 1 or 2 new voltage is the same as the current one.
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Voltage processor 1 or 2 transaction is done.
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Slave address in an I
2
C frame sent by the voltage controller not acknowledged by the power IC device
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Register address in an I
2
C frame sent by the voltage controller not acknowledged by the power IC
device
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Last byte of an I
2
C frame issued from the bypass port or the voltage manager FSM ports sent by the
voltage controller not acknowledged by the power IC device
The end-of-on time period and end-of-off time period events of the event generator module are sources of
interrupts to the MPU processor (the corresponding bits in the
are set to 1). The
end-of-off time period is the source of wake-up events on the MPU domain.
The MPU can force a sleep or wake-up transition on some domains (SGX, USBHOST, IVA2, PER, DSS,
CAM, NEON, EMU). The PRM triggers the MPU interrupt when the domain enters a power state. The
software must clear the CM_CLKSTCTRL_<domain_name> register only after getting the interrupt. If the
software clears this bit before getting the interrupt, the interrupt never occurs, regardless of whether the
transition occurs.
An interrupt for a peripheral with wake-up capability is enabled when the wake-up enable bit
(PM_WKEN_<domain_name> register type) and group select bit
(PM_<processor_name>GRPSEL_<domain_name> type of register) are set to 1.
The PRM triggers its interrupt line on the I/O daisy chain wake-up event. This wake-up event is enabled
by setting the corresponding bit in the PRCM.
register to 1.
The PRM triggers the MPU interrupt as long as the DPLL recalibration flag is set and the corresponding
interrupt enable bit in the PRM_IRQENABLE_<processor_name> register is set to 1. The recalibration flag
is set by the DPLL and remains active if the DPLL is not reinitialized.
398
Power, Reset, and Clock Management
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
