Wake-up
request
Idle mode edge detection
OR32
Debouncing
Debouncing enable
Edge detection control
Wake-up enable
Interrupt
status
register 2
Interrupt
status
register 1
32
I/O pins
gpif-008
Public Version
www.ti.com
General-Purpose Interface Functional Description
Figure 25-7. Asynchronous Path
•
The blocks handling the internal clock (clock gating) and managing the sleep mode
request/acknowledge protocol (enabling the synchronous path in active mode and the asynchronous
path in idle mode).
25.4.1 Operational Description
25.4.1.1 Interrupt and Wake-Up Features
25.4.1.1.1 Synchronous Path: Interrupt Request Generation
The general-purpose interface has 12 interrupt lines (two interrupt lines per GPIO module instance). The
12 interrupt signals are GPIOi_MPU_IRQ (used by the MPU subsystem) and GPIOi_IVA2_IRQ (used by
the IVA2.2 subsystem), where i = 1, 2, 3, 4, 5, and 6.
Synchronous interrupt requests from each channel are processed by two identical interrupt generation
submodules used independently by the IVA2.2 subsystem and the MPU subsystem. Each submodule
controls its own synchronous interrupt request line and has its own interrupt-enable
(GPIOi.
or GPIOi.
) and interrupt-status
or GPIOi.
) registers. The interrupt-enable register
selects the channel(s) considered for the interrupt request generation, and the interrupt-status register
determines which channel(s) activate the interrupt request. Event detection on GPIO channels is reflected
in the interrupt-status registers independent of the content of the interrupt-enable registers.
In active mode, when the GPIO configuration registers are set to enable the interrupt generation (see
, Interrupt and Wakeup), a synchronous path samples the transitions and levels on the input
GPIO with the internally gated interface clock (see
, Module Power Saving). When an
event matches the programmed settings (see
, Interrupt and Wakeup), the corresponding
bit in the interrupt-status register is set to 1 and, on the following interface clock cycle, the interrupt lines 1
and/or 2 are activated (depending on the interrupt-enable registers).
Because of the sampling operation, the minimum pulse width on the input GPIO to trigger a synchronous
interrupt request is two times the internally gated interface clock period (the internally gated interface clock
period equals N times the interface clock period; see
, Module Power Saving). This
minimum pulse width must be met before and after any expected level transition detection. For level
detection, the selected level must be stable for at least two times the internally-gated interface clock
period to trigger a synchronous interrupt.
Because the module is synchronous, latency is minimal between the expected event occurrence and the
activation of the interrupt line(s). This latency must not exceed four internally gated interface clock cycles
plus one interface clock cycle when the debounce feature is not used.
When the debounce feature is active, the latency depends on the value of the debouncing time register
(GPIOi.
) (see
, Debouncing Time) and is less than three
internally gated interface clock cycles plus two interface clock cycle, plus
GPIOi.
register value debounce clock cycles plus three debounce clock cycles.
3477
SWPU177N – December 2009 – Revised November 2010
General-Purpose Interface
Copyright © 2009–2010, Texas Instruments Incorporated
