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General-Purpose Interface Integration
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When GPIO is configured in force-idle mode (GPIOi.
[4:3] IDLEMODE bit field [00])
and receives an idle request from the PRCM module for GPIO2 to GPIO6: The corresponding bits in
the PRCM.CM_FCLKEN_PER and PRCM.CM_ICLKEN_PER registers cleared to 0, or the
corresponding bit in PRCM.CM_AUTOIDLE_PER bit set to 1 and L4 interface clock idle transitions; for
GPIO1: the PRCM.CM_FCLKEN_ WKUP[3] EN_GPIO1 bit cleared to 0, the
PRCM.CM_ICLKEN_WKUP[3] EN_GPIO1 bit cleared to 0, or the PRCM.CM_AUTOIDLE_WKUP[3]
AUTO_ GPIO1 bit set to 1 and the L4 interface clock idle transitions), GPIO waits unconditionally for
an active system clock gating by the PRCM module. (This occurs only when all peripherals supplied by
the same L4 interface clock domain are also ready for idle.)
When in idle mode (that is, when the PRCM module gates the interface clock), the module (in inactive
mode) has no activity, the interface clock paths are gated, an interrupt cannot be generated, and the
wake-up feature is totally inhibited.
•
No-idle mode
When GPIO is configured in no-idle mode (GPIOi.GPIO_ SYSCONFIG[4:3] IDLEMODE bit field [01])
and receives an idle request from the PRCM module (for GPIO2 to GPIO6: The corresponding bits in
the PRCM.CM_FCLKEN_PER and PRCM.CM_ICLKEN_PER registers cleared to 0 or the
corresponding bit in the PRCM.CM_AUTOIDLE_PER bit set to 1 and L4 interface clock idle transitions;
for GPIO1: the PRCM.CM_FCLKEN_ WKUP[3] EN_GPIO1 bit cleared to 0,
PRCM.CM_ICLKEN_WKUP[3] EN_GPIO1 bit cleared to 0, or PRCM.CM_AUTOIDLE_WKUP[3]
AUTO_ GPIO1 bit set to 1 and L4 interface clock idle transitions), GPIO does not go to idle mode and
the idle acknowledge is never sent.
NOTE:
The GPIO2 to GPIO6 idle state can be checked by reading the corresponding status bits in
the PRCM.CM_IDLEST_PER register (0: Active; 1: Idle) and is idle only when GPIO2 to
GPIO6 are configured in smart-idle mode and have asserted their idle acknowledge.
The GPIO1 idle state can be checked by the PRCM.CM_IDLEST_WKUP[3] ST_GPIO1 bit
(0: Idle, 1: active) and is idle only when GPIO1 is configured in smart-idle mode and has
asserted its idle acknowledge.
GPIO2 to GPIO6 wake-up status can be checked by accessing the corresponding bits in the
PRCM.PM_WKST_PER register (read 0: No wakeup occurred; read 1: Wakeup occurred;
write 1: Status bit reset).
The GPIO1 wake-up status can also be checked by the PRCM.PM_WKST_WKUP[3]
ST_GPIO1 bit (read 0: No wake-up occurred; read 1: Wakeup occurred; write 1: Status bit
reset).
25.3.1.1.4.4 Module Power Saving
GPIO has local power management by internal clock-gating features:
•
Internal interface clock gating: The clock for the L4 interconnect logic can be gated when the module is
not accessed, if the GPIOi.
[0] AUTOIDLE bit is set. Otherwise, this logic is
free-running on the interface clock.
•
Clock gating for the input data sample logic: The clock for the input data sample logic can be gated
when the data in the register is not accessed.
•
Clock gating for the event detection logic: Each GPIO module implements four clock groups used for
the logic in synchronous events detection. Each group of eight input GPIO pins has a separate enable
signal depending on the edge/level detection register setting. If a group requires no detection, the
corresponding clock is gated off (see
, Power Saving by Grouping the Edge/Level
Detection). All channels are also gated using a one-out-of-N scheme. N is the GPIOi.
GATINGRATIO bit field; it can take the values 1 (b00), 2 (0b01), 4 (b10), or 8 (0b11). The interface
clock is enabled for this logic one cycle every N cycles. When N equals 1, there is no gating and this
logic is free-running on the interface clock. When N is 2, 4, or 8, this logic runs at a frequency equal to
the interface clock frequency divided by N.
•
Inactive mode: All internal clock paths are gated.
•
Disabled mode: All internal clock paths not used for the L4 interconnect are gated. The
GPIOi.
[0] DISABLEMODULE bit controls a clock-gating feature at the module level. When
3472
General-Purpose Interface
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
